公开(公告)号：US11468929B2

公开(公告)日：2022-10-11

申请号：US17235297

申请日：2021-04-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY, LIMITED

发明人： Yi-Tzu Chen ,  Ching-Wei Wu ,  Hau-Tai Shieh ,  Hung-Jen Liao ,  Fu-An Wu ,  He-Zhou Wan ,  XiuLi Yang

IPC分类号： G11C16/10 ,  G11C7/22 ,  G11C7/12 ,  G11C7/14 ,  G11C7/10

摘要： A memory circuit includes a NAND logic gate, a first N-type transistor, a second N-type transistor, a first inverter and a first latch. The NAND logic gate is configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The first N-type transistor is coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The second N-type transistor is coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The first inverter is coupled to the NAND logic gate, and configured to output a data signal inverted from the first signal. The first latch is coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.

公开(公告)号：US11715505B2

公开(公告)日：2023-08-01

申请号：US17816090

申请日：2022-07-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY, LIMITED

发明人： Yi-Tzu Chen ,  Ching-Wei Wu ,  Hau-Tai Shieh ,  Hung-Jen Liao ,  Fu-An Wu ,  He-Zhou Wan ,  XiuLi Yang

IPC分类号： G11C7/22 ,  G11C7/10 ,  G11C7/12 ,  G11C7/14

CPC分类号： G11C7/222 ,  G11C7/106 ,  G11C7/1048 ,  G11C7/1087 ,  G11C7/12 ,  G11C7/14

摘要： A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a second N-type transistor coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.

公开(公告)号：US20240185911A1

公开(公告)日：2024-06-06

申请号：US18443979

申请日：2024-02-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Tzu Chen ,  Ching-Wei Wu ,  Hau-Tai Shieh ,  Hung-Jen Liao

IPC分类号： G11C11/408 ,  G11C5/02 ,  G11C5/06 ,  G11C11/4093

CPC分类号： G11C11/4085 ,  G11C5/025 ,  G11C5/06 ,  G11C11/4093

摘要： Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.

公开(公告)号：US20230267989A1

公开(公告)日：2023-08-24

申请号：US18306762

申请日：2023-04-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Tzu Chen ,  Ching-Wei Wu ,  Hau-Tai Shieh ,  Hung-Jen Liao

IPC分类号： G11C11/408 ,  G11C5/02 ,  G11C5/06 ,  G11C11/4093

CPC分类号： G11C11/4085 ,  G11C5/025 ,  G11C5/06 ,  G11C11/4093

摘要： Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.

公开(公告)号：US20230245677A1

公开(公告)日：2023-08-03

申请号：US18161627

申请日：2023-01-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Tzu Chen ,  Hau-Tai Shieh ,  Che-Ju Yeh

IPC分类号： G11B5/09 ,  G06F17/16 ,  G06N3/063 ,  G11B5/31 ,  G11C11/54

CPC分类号： G11B5/09 ,  G06F17/16 ,  G06N3/063 ,  G11B5/3146 ,  G11C11/54

摘要： A method of designing a circuit is provided. The method includes: providing a circuit; selecting a first NMOS fin field-effect transistor (FinFET) in the circuit; and replacing the first NMOS FinFET having a first fin number with a second NMOS FinFET having a second fin number and a third NMOS FinFET having a third fin number, wherein the sum of the second fin number and the third fin number is equal to the first fin number.

公开(公告)号：US20220284941A1

公开(公告)日：2022-09-08

申请号：US17824260

申请日：2022-05-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Che-Ju Yeh ,  Hau-Tai Shieh ,  Yi-Tzu Chen

IPC分类号： G11C11/4072 ,  G11C5/06 ,  G11C5/14 ,  G11C11/4074

摘要： A memory device includes an array of memory cells and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit may be configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells. Inserting a switch device across the different power domains to achieve the same sequential wake-up path for the peripheral circuits connected to different power domains reduces peak current.

公开(公告)号：US20210397773A1

公开(公告)日：2021-12-23

申请号：US17226428

申请日：2021-04-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Tzu Chen ,  Hau-Tai Shieh ,  Che-Ju Yeh

IPC分类号： G06F30/392 ,  H01L27/092 ,  H01L27/11 ,  G11C11/418

摘要： A method of designing a circuit is provided. The method includes: providing a circuit; selecting a first NMOS fin field-effect transistor (FinFET) in the circuit; and replacing the first NMOS FinFET having a first fin number with a second NMOS FinFET having a second fin number and a third NMOS FinFET having a third fin number, wherein the sum of the second fin number and the third fin number is equal to the first fin number.

公开(公告)号：US09058899B2

公开(公告)日：2015-06-16

申请号：US14083249

申请日：2013-11-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien-Yuan Chen ,  Yi-Tzu Chen ,  Hau-Tai Shieh ,  Tsung-Yung Jonathan Chang

IPC分类号： G11C11/00 ,  G11C11/417 ,  G11C11/412 ,  G11C11/413

CPC分类号： G11C11/417 ,  G11C11/412 ,  G11C11/413

摘要： Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.

摘要翻译： SRAM单元的示例性实施例，用于SRAM系统的新的控制单元以及SRAM系统的实施例在此被描述。 SRAM单元被配置为接收具有与第一输入电压信号不同的值的第一输入电压信号和第二输入电压信号，并且保持第一存储值信号和第二存储值信号。 控制电路被配置为接收第一输入电压信号和第二输入电压信号，并且由睡眠信号，选择信号和数据输入信号控制，使得控制电路的输出对数据是敏感的 输入信号。 SRAM系统包括多个SRAM单元，控制所公开的控制电路，其中SRAM单元分别具有由数据输入信号及其补码信号控制的两个输入电压信号。

公开(公告)号：US20140233303A1

公开(公告)日：2014-08-21

申请号：US14266457

申请日：2014-04-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yi-Tzu Chen ,  Wei-jer Hsieh ,  Tsai-Hsin Lai ,  Ling-Fang Hsu ,  Hau-Tai Shieh

IPC分类号： G11C11/418

CPC分类号： G11C11/418 ,  G11C7/1012 ,  G11C7/18 ,  G11C11/413

摘要： An SRAM multiplexing apparatus comprise a plurality of local multiplexers and a global multiplexer. Each local multiplexer is coupled to a memory bank. The global multiplexer has a plurality of inputs, each of which is coupled to a corresponding output of the plurality of local multiplexers. In response to a decoded address in a read operation, an input of a local multiplexer is forwarded to a corresponding input of the global multiplexer. Similarly, the decoded address allows the global multiplexer to forward the input signal to a data out port via a buffer.

摘要翻译： SRAM多路复用装置包括多个本地多路复用器和全局多路复用器。 每个本地多路复用器耦合到存储体。 全局多路复用器具有多个输入，每个输入耦合到多个本地多路复用器的相应输出端。 响应于读操作中的解码地址，本地多路复用器的输入被转发到全局多路复用器的相应输入端。 类似地，解码的地址允许全局多路复用器经由缓冲器将输入信号转发到数据输出端口。

公开(公告)号：US11670362B2

公开(公告)日：2023-06-06

申请号：US17687272

申请日：2022-03-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Tzu Chen ,  Ching-Wei Wu ,  Hau-Tai Shieh ,  Hung-Jen Liao

IPC分类号： G11C11/40 ,  G11C11/408 ,  G11C5/02 ,  G11C5/06 ,  G11C11/4093

CPC分类号： G11C11/4085 ,  G11C5/025 ,  G11C5/06 ,  G11C11/4093

摘要： Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.