公开(公告)号：US12154951B2

公开(公告)日：2024-11-26

申请号：US18178893

申请日：2023-03-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shahaji B. More ,  Cheng-Han Lee ,  Shih-Chieh Chang ,  Shih-Ya Lin ,  Chung-En Tsai ,  Chee-Wee Liu

IPC: H01L29/161 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: The present disclosure describes a semiconductor device includes a substrate, a buffer layer on the substrate, and a stacked fin structure on the buffer layer. The buffer layer can include germanium, and the stacked fin structure can include a semiconductor layer with germanium and tin. The semiconductor device further includes a gate structure wrapped around a portion of the semiconductor layer and an epitaxial structure on the buffer layer and in contact with the semiconductor layer. The epitaxial structure includes germanium and tin.

公开(公告)号：US20240312844A1

公开(公告)日：2024-09-19

申请号：US18673432

申请日：2024-05-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shahaji B. More ,  Cheng-Wei Chang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/417

CPC classification number: H01L21/823821 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/41791

Abstract: A semiconductor structure includes an n-type epitaxial source/drain feature (NEPI) and a p-type epitaxial source/drain feature (PEPI) over a substrate, wherein a top surface of the NEPI is lower than a top surface of the PEPI. The semiconductor structure further includes a metal compound feature disposed on the top surface of the NEPI and the top surface of the PEPI. The metal compound feature extends continuously from the top surface of the NEPI to the top surface of the PEPI. The semiconductor structure further includes a contact feature disposed on the metal compound feature and a via structure disposed over the contact feature.

公开(公告)号：US12027597B2

公开(公告)日：2024-07-02

申请号：US18108890

申请日：2023-02-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shahaji B. More ,  Jia-Ying Ma ,  Cheng-Han Lee

IPC: H01L29/417 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first source/drain epitaxial feature disposed in an NMOS region, a second source/drain epitaxial feature disposed in the NMOS region, a first dielectric feature disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a third source/drain epitaxial feature disposed in a PMOS region, a second dielectric feature disposed between the second source/drain epitaxial feature and the third source/drain epitaxial feature, and a conductive feature disposed over the first, second, and third source/drain epitaxial features and the first and second dielectric features.

公开(公告)号：US11973127B2

公开(公告)日：2024-04-30

申请号：US17089138

申请日：2020-11-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shahaji B. More ,  Shih-Chieh Chang ,  Cheng-Han Lee ,  Huai-Tei Yang

IPC: H01L29/417 ,  H01L21/265 ,  H01L21/3065 ,  H01L29/08 ,  H01L29/167 ,  H01L29/24 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66803 ,  H01L21/26513 ,  H01L21/3065 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/24 ,  H01L29/41791 ,  H01L29/66636 ,  H01L29/7851 ,  H01L29/7853

Abstract: Semiconductor structures and method for forming the same are provide. The semiconductor structure includes a fin structure protruding from a substrate and a gate structure formed across the fin structure. The semiconductor structure further includes an Arsenic-doped region formed in the fin structure and a source/drain structure formed over the Arsenic-doped region. In addition, a bottommost portion of the Arsenic-doped region is lower than a bottommost portion of the source/drain structure.

公开(公告)号：US20230299153A1

公开(公告)日：2023-09-21

申请号：US18319999

申请日：2023-05-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shahaji B. More ,  Chandrashekhar Prakash Savant

IPC: H01L29/40 ,  H01L21/28 ,  H01L29/49 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/401 ,  H01L21/28061 ,  H01L21/28079 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/495 ,  H01L29/4966

Abstract: A semiconductor structure includes a first transistor adjacent a second transistor. The first transistor includes a first gate metal layer over a gate dielectric layer, and the second transistor includes a second gate metal layer over the gate dielectric layer. The first and the second gate metal layers include different materials. The semiconductor structure further includes a first barrier disposed horizontally between the first gate metal layer and the second gate metal layer. One of the first and the second gate metal layers includes aluminum, and the first barrier has low permeability for aluminum. A bottom surface of the first gate metal layer is directly on a top surface of the first barrier.

公开(公告)号：US11670681B2

公开(公告)日：2023-06-06

申请号：US17207058

申请日：2021-03-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shahaji B. More ,  Shu Kuan ,  Cheng-Han Lee

IPC: H01L21/306 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/308 ,  H01L29/10 ,  H01L27/092 ,  H01L29/161 ,  H01L21/8238 ,  H01L23/544

CPC classification number: H01L29/1054 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L23/544 ,  H01L27/0924 ,  H01L27/0928 ,  H01L29/161 ,  H01L2223/54426

Abstract: A method includes forming an N well and a P well in a substrate; depositing a first layer having silicon over the N well and the P well; depositing a first dielectric layer over the first layer; forming a resist pattern over the first dielectric layer, the resist pattern providing an opening directly above the N well; etching the first dielectric layer and the first layer through the opening, leaving a first portion of the first layer over the N well; removing the resist pattern; and epitaxially growing a second layer having silicon germanium (SiGe) over the first portion of the first layer. The epitaxially growing the second layer includes steps of (a) performing a baking process, (b) depositing a silicon seed layer, and (c) depositing a SiGe layer over the silicon seed layer, wherein the steps (a), (b), and (c) are performed under about a same temperature.

公开(公告)号：US11581411B2

公开(公告)日：2023-02-14

申请号：US17171253

申请日：2021-02-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shahaji B. More ,  Jia-Ying Ma ,  Cheng-Han Lee

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/08 ,  H01L29/06 ,  H01L29/45 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/285

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first source/drain epitaxial feature disposed in an NMOS region, a second source/drain epitaxial feature disposed in the NMOS region, a first dielectric feature disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a third source/drain epitaxial feature disposed in a PMOS region, a second dielectric feature disposed between the second source/drain epitaxial feature and the third source/drain epitaxial feature, and a conductive feature disposed over the first, second, and third source/drain epitaxial features and the first and second dielectric features.

公开(公告)号：US11171220B2

公开(公告)日：2021-11-09

申请号：US16889452

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shahaji B. More ,  Cheng-Han Lee ,  Zheng-Yang Pan ,  Shih-Chieh Chang ,  Chun-Chieh Wang

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/10 ,  H01L29/78 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/84

Abstract: A method of forming a gate dielectric material includes forming a high-K dielectric material in a first region over a substrate, where forming the high-K dielectric material includes forming a first dielectric layer comprising hafnium over the substrate, and forming a second dielectric layer comprising lanthanum over the first dielectric layer.

公开(公告)号：US10734524B2

公开(公告)日：2020-08-04

申请号：US16505061

申请日：2019-07-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Yu Ma ,  Zheng-Yang Pan ,  Shahaji B. More ,  Shih-Chieh Chang ,  Cheng-Han Lee

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/485 ,  H01L29/08 ,  H01L29/165

Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.

公开(公告)号：US10672886B2

公开(公告)日：2020-06-02

申请号：US15722652

申请日：2017-10-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shahaji B. More ,  Cheng-Han Lee ,  Zheng-Yang Pan ,  Shih-Chieh Chang ,  Chun-Chieh Wang

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/51 ,  H01L29/10 ,  H01L29/78 ,  H01L21/28 ,  H01L21/8238

Abstract: A method of forming a gate dielectric material includes forming a high-K dielectric material in a first region over a substrate, where forming the high-K dielectric material includes forming a first dielectric layer comprising hafnium over the substrate, and forming a second dielectric layer comprising lanthanum over the first dielectric layer.