公开(公告)号：US20240266246A1

公开(公告)日：2024-08-08

申请号：US18641449

申请日：2024-04-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hao Chen ,  Po-Yuan Cheng ,  Pu Wang ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC分类号： H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L23/3675 ,  H01L21/4882 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/295 ,  H01L23/3185 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2224/214 ,  H01L2225/06558 ,  H01L2225/06589 ,  H01L2924/1715

摘要： A manufacturing method of a package structure includes: forming a first package component over a temporary carrier, wherein the first package component comprises a semiconductor die encapsulated by an insulating encapsulation material that comprises a base layer and a plurality of fillers inside the base layer; de-bonding the temporary carrier to expose a rear side of the semiconductor die, wherein during the de-bonding, a portion of the fillers is accessibly revealed from the base layer to form an insulating encapsulation; forming a metallic layer on the rear side of the semiconductor die and the portion of the fillers of the insulating encapsulation; and coupling a heat dissipating component to the first package component at least through the metallic layer.

公开(公告)号：US11996345B2

公开(公告)日：2024-05-28

申请号：US17458600

申请日：2021-08-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hao Chen ,  Po-Yuan Cheng ,  Pu Wang ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC分类号： H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L23/3675 ,  H01L21/4882 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/295 ,  H01L23/3185 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2224/214 ,  H01L2225/06558 ,  H01L2225/06589 ,  H01L2924/1715

摘要： A package structure includes a first semiconductor die, a first insulating encapsulation, a thermal coupling structure, and a heat dissipating component thermally coupled to the first semiconductor die through the thermal coupling structure. The first semiconductor die includes an active side, a rear side, and a sidewall connected to the active side and the rear side. The first insulating encapsulation extends along the sidewall of the first semiconductor die and includes a first side substantially leveled with the active side, a second side opposite to the first side, and topographic features at the second side. The thermal coupling structure includes a metallic layer overlying and the rear side of the first semiconductor die and the topographic features of the first insulating encapsulation. A manufacturing method of a package structure is also provided.

公开(公告)号：US11894287B2

公开(公告)日：2024-02-06

申请号：US18181552

申请日：2023-03-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hao Chen ,  Chin-Fu Kao ,  Li-Hui Cheng ,  Szu-Wei Lu ,  Chih-Chien Pan

IPC分类号： H01L23/42 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L27/06 ,  H01L23/538

CPC分类号： H01L23/42 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/3185 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/14 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L25/0655 ,  H01L27/0688 ,  H01L2224/2958

摘要： Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.

公开(公告)号：US20230360995A1

公开(公告)日：2023-11-09

申请号：US18356227

申请日：2023-07-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hao Chen ,  Chin-Fu Kao ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC分类号： H01L23/367 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L21/56

CPC分类号： H01L23/3675 ,  H01L23/3185 ,  H01L24/16 ,  H01L21/4853 ,  H01L21/4882 ,  H01L21/6835 ,  H01L21/563 ,  H01L2924/18161 ,  H01L2221/68354 ,  H01L2224/16227

摘要： A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer.

公开(公告)号：US11804468B2

公开(公告)日：2023-10-31

申请号：US17149737

申请日：2021-01-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hao Chen ,  Chih-Chien Pan ,  Pu Wang ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC分类号： H01L23/00 ,  H01L21/52 ,  H01L21/48 ,  H01L21/67 ,  H01L23/40

CPC分类号： H01L24/75 ,  H01L21/4882 ,  H01L21/52 ,  H01L21/67121 ,  H01L21/67126 ,  H01L24/83 ,  H01L2023/405 ,  H01L2023/4062 ,  H01L2023/4087 ,  H01L2224/7555 ,  H01L2224/83208

摘要： A jig for manufacturing a semiconductor package includes a bottom piece and an upper piece. The bottom piece includes a base, a support plate, and at least one elastic connector. The support plate is located in a central region of the base. The at least one elastic connector is interposed between the support plate and the base. The upper piece includes a cap and outer flanges. The cap overlays the support plate when the upper piece is disposed on the bottom piece. The outer flanges are disposed at edges of the cap, connected with the cap. The outer flanges contact the base of the bottom piece when the upper piece is disposed on the bottom piece. The cap includes an opening which is a through hole. When the upper piece is disposed on the bottom piece, a vertical projection of the opening falls entirely on the support plate.

公开(公告)号：US11049763B2

公开(公告)日：2021-06-29

申请号：US16694406

申请日：2019-11-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Kai Chen ,  Jung-Hau Shiu ,  Chia Cheng Chou ,  Chung-Chi Ko ,  Tze-Liang Lee ,  Chih-Hao Chen ,  Shing-Chyang Pan

IPC分类号： H01L21/768 ,  H01L21/311

摘要： A method includes forming a carbon-containing layer with a carbon atomic percentage greater than about 25 percent over a first hard mask layer, forming a capping layer over the carbon-containing layer, forming a first photo resist over the capping layer, and etching the capping layer and the carbon-containing layer using the first photo resist as a first etching mask. The first photo resist is then removed. A second photo resist is formed over the capping layer. The capping layer and the carbon-containing layer are etched using the second photo resist as a second etching mask. The second photo resist is removed. A third photo resist under the carbon-containing layer is etched using the carbon-containing layer as etching mask. A dielectric layer underlying the third photo resist is etched to form via openings using the third photo resist as etching mask. The via openings are filled with a conductive material.

公开(公告)号：US20190067022A1

公开(公告)日：2019-02-28

申请号：US15871675

申请日：2018-01-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jiann-Horng Lin ,  Cheng-Li Fan ,  Chih-Hao Chen

IPC分类号： H01L21/308 ,  H01L21/768

摘要： A method for reducing wiggling in a line includes forming a silicon patterning layer over a substrate and depositing a mask layer over the silicon patterning layer. The mask layer is patterned to form one or more openings therein. The mask layer is thinned and the one or more openings are widened, to provide a smaller height-to-width ratio. The pattern of the mask layer is then used to pattern the silicon patterning layer. The silicon patterning layer is used, in turn, to pattern a target layer where a metal line will be formed.

公开(公告)号：US20160118347A1

公开(公告)日：2016-04-28

申请号：US14987217

申请日：2016-01-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd

发明人： Cha-Hsin Chao ,  Chih-Hao Chen ,  Hsin-Yi Tsai

IPC分类号： H01L23/532 ,  H01L23/528 ,  H01L23/522

CPC分类号： H01L23/53295 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer, a hard mask layer over the dielectric layer, and a capping layer over the hard mask layer. A multi-patterning process is performed to form an interconnect using the capping layer as a mask to form an opening for the interconnect.

摘要翻译： 提供了一种用于半导体器件的系统和方法。 一个实施例包括电介质层，电介质层上的硬掩模层和硬掩模层上的覆盖层。 执行多图案化工艺以形成使用覆盖层作为掩模的互连，以形成用于互连的开口。

公开(公告)号：US09147602B2

公开(公告)日：2015-09-29

申请号：US14493992

申请日：2014-09-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chii-Ping Chen ,  Chih-Hao Chen

IPC分类号： H01L21/76 ,  H01L21/768 ,  H01L23/522 ,  H01L23/538

CPC分类号： H01L21/7682 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5384 ,  H01L2224/16225

摘要： A method of making an integrated circuit includes forming an interconnect structure in an opening in a dielectric layer. The method further includes forming an air gap between the dielectric layer and the interconnect structure, where a first liner layer along a bottom portion of a sidewall of the opening of the dielectric layer is under the air gap, and a top portion of the first liner layer is below a lowest portion of the air gap.

摘要翻译： 制造集成电路的方法包括在电介质层的开口中形成互连结构。 该方法还包括在电介质层和互连结构之间形成气隙，其中沿着电介质层的开口的侧壁的底部的第一衬垫层位于气隙下方，并且第一衬垫的顶部 层低于气隙的最低部分。

公开(公告)号：US20140300000A1

公开(公告)日：2014-10-09

申请号：US13963731

申请日：2013-08-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cha-Hsin Chao ,  Chih-Hao Chen ,  Hsin-Yi Tsai

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/53295 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer, a hard mask layer over the dielectric layer, and a capping layer over the hard mask layer. A multi-patterning process is performed to form an interconnect using the capping layer as a mask to form an opening for the interconnect.

摘要翻译： 提供了一种用于半导体器件的系统和方法。 一个实施例包括电介质层，电介质层上的硬掩模层和硬掩模层上的覆盖层。 执行多图案化工艺以形成使用覆盖层作为掩模的互连，以形成互连的开口。