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    TRANSISTOR ISOLATION STRUCTURES
    4.
    发明公开
    TRANSISTOR ISOLATION STRUCTURES 审中-公开

    公开(公告)号：US20240145579A1

    公开(公告)日：2024-05-02

    申请号：US18409421

    申请日：2024-01-10

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yu-Yun PENG ,  Fu-Ting YEN ,  Keng-Chu LIN

    IPC分类号： H01L29/66 ,  H01L29/06

    CPC分类号： H01L29/66553 ,  H01L29/0653 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/78696

    摘要： The present disclosure is directed to method for the fabrication of spacer structures between source/drain (S/D) epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form cavities. Further, depositing a spacer material on the fin structure to fill the cavities and removing a portion of the spacer material in the cavities to form an opening in the spacer material. In addition, the method includes forming S/D epitaxial structures on the substrate to abut the fin structure and the spacer material so that sidewall portions of the S/D epitaxial structures seal the opening in the spacer material to form an air gap in the spacer material.

    SEMICONDUCTOR DEVICE STRUCTURE WITH GATE SPACER
    5.
    发明申请
    SEMICONDUCTOR DEVICE STRUCTURE WITH GATE SPACER 有权

    公开(公告)号：US20210118677A1

    公开(公告)日：2021-04-22

    申请号：US17117393

    申请日：2020-12-10

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Guan-Yao TU ,  Yu-Yun PENG

    IPC分类号： H01L21/02 ,  H01L29/49 ,  H01L29/51 ,  H01L23/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

    摘要： A s semiconductor device structure is provided. The structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The structure also includes a spacer element extending along a sidewall of the gate stack. The spacer element has a first portion, a second portion, a third portion, and a fourth portion. Each of the first portion, the second portion, the third portion, and the fourth portion conformally extends along the sidewall of the gate stack. The second portion is sandwiched between the first portion and the third portion, and the third portion is sandwiched between the second portion and the fourth portion. Each of the first portion and the third portion has a first atomic concentration of carbon, and each of the second portion and the fourth portion has a second atomic concentration of carbon. The second atomic concentration of carbon is different than the first atomic concentration of carbon.

    METHOD OF MAKING INTERCONNECT STRUCTURE
    6.
    发明申请
    METHOD OF MAKING INTERCONNECT STRUCTURE 有权
    制造互连结构的方法

    公开(公告)号：US20150011084A1

    公开(公告)日：2015-01-08

    申请号：US14494211

    申请日：2014-09-23

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Po-Cheng SHIH ,  Yu-Yun PENG ,  Chia Cheng CHOU ,  Joung-Wei LIOU

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76832 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/02304 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76835 ,  H01L21/76846 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of making a semiconductor device including forming a first adhesion layer over a substrate. The method further includes forming a second adhesion layer over the first adhesion layer, where the second adhesion layer is formed using an inert gas with a first flow rate under a first RF power. Additionally, the method includes forming a low-k dielectric layer over the second adhesion layer, where the low-k dielectric layer is formed using the inert gas with a second flow rate under a second RF power under at least one of the following two conditions: 1) the second flow rate is different from the first flow rate; or 2) the second RF power is different from the first RF power. Furthermore, the method includes forming an opening in the dielectric layer, the second adhesion layer, and the first adhesion layer. Additionally, the method includes forming a conductor in the opening.

    摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成第一粘附层。 该方法还包括在第一粘附层上形成第二粘附层，其中第二粘合层使用在第一RF功率下的第一流量的惰性气体形成。 另外，该方法包括在第二粘合层上形成低k电介质层，其中在下列两个条件中的至少一个条件下，在第二RF功率下使用具有第二流量的惰性气体形成低k电介质层 ：1）第二流量与第一流量不同; 或2）第二RF功率不同于第一RF功率。 此外，该方法包括在电介质层，第二粘合层和第一粘合层中形成开口。 另外，该方法包括在开口中形成导体。

    INTERCONNECT STRUCTURE AND METHODS OF FORMING THE SAME
    9.
    发明申请
    INTERCONNECT STRUCTURE AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20220352073A1

    公开(公告)日：2022-11-03

    申请号：US17473573

    申请日：2021-09-13

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Yu-Yun PENG ,  Keng-Chu LIN

    IPC分类号： H01L23/535 ,  H01L23/373 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

    摘要： An interconnect structure, along with methods of forming such, are described. In some embodiments, the structure includes a first dielectric layer disposed over one or more devices, a first conductive feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first conductive feature, and a second conductive feature disposed in the second dielectric layer. The second conductive feature is electrically connected to the first conductive feature. The structure further includes a heat dissipation layer disposed between the first and second dielectric layers, and the heat dissipation layer partially surrounds the second conductive feature and is electrically isolated from the first and second conductive features.