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公开(公告)号:US10961114B2
公开(公告)日:2021-03-30
申请号:US16426575
申请日:2019-05-30
发明人: Ching-Kai Shen , Yi-Chuan Teng , Wei-Chu Lin , Hung-Wei Liang , Jung-Kuo Tu
摘要: The present disclosure provides a semiconductor structure, including a sensing substrate, a capping substrate over the sensing substrate, the capping substrate having a first surface facing toward the sensing substrate and a second surface facing away from the sensing substrate, wherein the capping substrate comprises a through hole extending from the first surface to the second surface, a spacer between the sensing substrate and the capping substrate, the spacer, the sensing substrate, and the capping substrate forming a cavity connecting with the through hole, and a sealing structure at the second surface and aligning with the through hole, wherein the sealing structure comprises a metal layer and a dielectric layer.
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公开(公告)号:US20230399226A1
公开(公告)日:2023-12-14
申请号:US17835175
申请日:2022-06-08
发明人: Fan Hu , Wen-Chuan Tai , Li-Chun Peng , Hsiang-Fu Chen , Ching-Kai Shen , Hung-Wei Liang , Jung-Kuo Tu
CPC分类号: B81B7/008 , B81C3/001 , B81C2201/013 , B81B2203/033 , B81B2207/015
摘要: The present disclosure relates to an integrated chip including a semiconductor device substrate and a plurality of semiconductor devices arranged along the semiconductor device substrate. A micro-electromechanical system (MEMS) layer overlies the semiconductor device substrate. The MEMS layer includes a first moveable mass and a second moveable mass. A capping layer overlies the MEMS layer. The capping layer has a first lower surface directly over the first moveable mass and a second lower surface directly over the second moveable mass. An outgas layer is on the first lower surface and directly between the first pair of sidewalls. A lower surface of the outgas layer delimits a first cavity in which the first moveable mass is arranged. The second lower surface of the capping layer delimits a second cavity in which the second moveable mass is arranged.
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公开(公告)号:US12074110B2
公开(公告)日:2024-08-27
申请号:US17815242
申请日:2022-07-27
发明人: Ching-Kai Shen , Yi-Chuan Teng , Wei-Chu Lin , Hung-Wei Liang , Jung-Kuo Tu
IPC分类号: H01L23/532 , H01L21/768 , H01L23/31 , H01L23/34 , H01L23/48
CPC分类号: H01L23/53295 , H01L21/76898 , H01L23/3171 , H01L23/34 , H01L23/481
摘要: A method for forming a semiconductor device includes receiving a first bonded to a second substrate by a dielectric layer, wherein a conductive layer is disposed in the dielectric layer and a cavity is formed between the first substrate, the second substrate and the dielectric layer; forming a via opening in the second substrate to expose the conductive layer and a vent hole in the substrate to couple to the cavity; forming a first buffer layer covering sidewalls of the via opening and a second buffer layer covering sidewalls of the vent hole; and forming a connecting structure in the via opening and a sealing structure to seal the vent hole.
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4.
公开(公告)号:US11772960B2
公开(公告)日:2023-10-03
申请号:US17209098
申请日:2021-03-22
发明人: Ching-Kai Shen , Yi-Chuan Teng , Wei-Chu Lin , Hung-Wei Liang , Jung-Kuo Tu
CPC分类号: B81B7/0041 , B81C1/00293 , B81B2201/0235 , B81B2201/0242 , B81B2207/07 , B81C2203/0145
摘要: The present disclosure provides a method for fabricating a semiconductor structure, including bonding a capping substrate over a sensing substrate, forming a through hole traversing the capping substrate, forming a dielectric layer over the capping substrate under a first vacuum level, and forming a metal layer over the dielectric layer under a second vacuum level, wherein the second vacuum level is higher than the first vacuum level.
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5.
公开(公告)号:US11462478B2
公开(公告)日:2022-10-04
申请号:US16426543
申请日:2019-05-30
发明人: Ching-Kai Shen , Yi-Chuan Teng , Wei-Chu Lin , Hung-Wei Liang , Jung-Kuo Tu
IPC分类号: H01L23/532 , H01L23/31 , H01L21/768 , H01L23/48 , H01L23/34
摘要: A semiconductor device includes a first substrate; a dielectric layer disposed over the first substrate and a conductive layer disposed in the dielectric layer; a second substrate bonded to the dielectric layer, wherein the second substrate has a first surface facing the first substrate and a second surface opposite to the first substrate; a connecting structure penetrating the second substrate and a portion of the dielectric layer and electrically coupled to the conductive layer; a vent hole penetrating the second substrate from the second surface to the first surface; a first buffer layer between the connecting structure and the dielectric layer and between the connecting structure and the second substrate; and a second buffer layer covering sidewalls of the vent hole and exposed through the first surface of the second substrate. The first buffer layer and the second buffer layer include a same material and a same thickness.
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