公开(公告)号：US20250063744A1

公开(公告)日：2025-02-20

申请号：US18939603

申请日：2024-11-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Li Cheng ,  Jyun-Ying Lin ,  Alexander Kalnitsky ,  Shih-Fen Huang ,  Shu-Hui Su ,  Ting-Chen Hsu ,  Tuo-Hsin Chien ,  Felix Ying-Kit Tsui ,  Shi-Min Wu ,  Yu-Chi Chang

IPC: H01L21/02 ,  H01L21/3213 ,  H01L21/764 ,  H01L23/00 ,  H01L29/66 ,  H01L29/94

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a substrate comprising first opposing sidewalls defining a first trench and second opposing sidewalls defining a second trench laterally offset from the first trench. A stack of layers comprises a plurality of conductive layers and a plurality of dielectric layers alternatingly stacked with the conductive layers. The stack of layers comprises a first segment in the first trench and a second segment in the second trench. A first lateral distance between the first segment and the second segment aligned with a first surface of the substrate is greater than a second lateral distance between the first segment and the second segment below the first surface of the substrate.

公开(公告)号：US20240290541A1

公开(公告)日：2024-08-29

申请号：US18659337

申请日：2024-05-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Anderson Lin ,  Chun-Ren Cheng ,  Chi-Yuan Shih ,  Shih-Fen Huang ,  Yi-Chuan Teng ,  Yi Heng Tsai ,  You-Ru Lin ,  Yen-Wen Chen ,  Fu-Chun Huang ,  Fan Hu ,  Ching-Hui Lin ,  Yan-Jie Liao

IPC: H01G4/012 ,  H01G4/12 ,  H01G4/228 ,  H01L21/311 ,  H01L21/3213 ,  H10N30/30 ,  H10N30/50 ,  H10N30/87

CPC classification number: H01G4/012 ,  H01G4/12 ,  H01G4/228 ,  H01L21/31111 ,  H01L21/32139 ,  H01L28/60 ,  H10N30/302 ,  H10N30/501 ,  H10N30/508 ,  H10N30/872

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first conductive structure and a second conductive structure. A dielectric structure is arranged between the first conductive structure and the second conductive structure. The dielectric structure comprises an upper region over a lower region. The lower region comprises a first lateral surface and a second lateral surface on opposing sides of the upper region. A passivation layer overlies the second conductive structure and the dielectric structure. The passivation layer comprises a lateral segment contacting the first lateral surface. A height of the lateral segment is greater than a height of the upper region. A top surface of the lateral segment is below a top surface of the passivation layer.

公开(公告)号：US20240099147A1

公开(公告)日：2024-03-21

申请号：US18513918

申请日：2023-11-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Yuan Shih ,  Shih-Fen Huang ,  You-Ru Lin ,  Yan-Jie Liao

IPC: H10N39/00 ,  H10N30/074 ,  H10N30/20

CPC classification number: H10N39/00 ,  H10N30/074 ,  H10N30/206

Abstract: In some embodiments, the present disclosure relates to a method in which a first set of one or more voltage pulses is applied to a piezoelectric device over a first time period. During the first time period, the method determines whether a performance parameter of the piezoelectric device has a first value that deviates from a reference value by more than a predetermined value. Based on whether the first value deviates from the reference value by more than the predetermined value, the method selectively applies a second set of one or more voltage pulses to the piezoelectric device over a second time period. The second time period is after the first time period and the second set of one or more voltage pulses differs in magnitude and/or polarity from the first set of one or more voltage pulses.

公开(公告)号：US11581308B2

公开(公告)日：2023-02-14

申请号：US16923925

申请日：2020-07-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Fu-Chun Huang ,  Ching-Hui Lin ,  Chun-Ren Cheng ,  Shih-Fen Huang ,  Alexander Kalnitsky

IPC: H01L27/07 ,  H01L29/06 ,  H01L49/02 ,  H01L21/8234 ,  H01L21/762

Abstract: A method for manufacturing a semiconductor structure is provided, wherein the method includes the following operations. A substrate having a transistor is received, wherein the transistor includes a channel region and a gate on a first side of the channel region. A second side of the channel region of the transistor is exposed, wherein the second side is opposite to the first side. A metal oxide is formed on the second side of the channel region of the transistor, wherein the metal oxide contacts the channel region and is exposed to the environment. A semiconductor structure and an operation of a semiconductor structure thereof are also provided.

公开(公告)号：US20220254871A1

公开(公告)日：2022-08-11

申请号：US17729321

申请日：2022-04-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Yuan Shih ,  Kai-Fung Chang ,  Shih-Fen Huang ,  Yan-Jie Liao

IPC: H01L49/02

Abstract: In some embodiments, the present disclosure relates to a method of forming a metal-insulator-metal (MIM) device. The method may be performed by depositing a bottom electrode layer over a substrate, depositing a dielectric layer over the bottom electrode layer, depositing a top electrode layer over the dielectric layer, and depositing a first titanium getter layer over the top electrode layer. The first titanium getter layer, the top electrode layer, and the dielectric layer are patterned to expose a peripheral portion of the bottom electrode layer. A passivation layer is deposited over the substrate, the first titanium getter layer, and the peripheral portion of the bottom electrode layer.

公开(公告)号：US20250006777A1

公开(公告)日：2025-01-02

申请号：US18470180

申请日：2023-09-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Heng Chen ,  Chi-Yuan Shih ,  Hsin-Li Cheng ,  Shih-Fen Huang ,  Tuo-Hsin Chien ,  Yu-Chi Chang

IPC: H01C17/075 ,  H01C7/00 ,  H01L23/522

Abstract: Resistors and method of forming the same are provided. A device structure according to the present disclosure includes a substrate, a first intermetal dielectric (IMD) layer over the substrate, a resistor that includes a first resistor layer over the first IMD layer, a second resistor layer over the first resistor layer, and a third resistor layer over the second resistor layer, a second IMD layer over the first IMD layer and the resistor, a first contact via extending through the second IMD layer and the third resistor layer and terminating in the first resistor layer, and a second contact via extending through the second IMD layer and the third resistor layer and terminating in the first resistor layer.

公开(公告)号：US12176387B2

公开(公告)日：2024-12-24

申请号：US18362146

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Li Cheng ,  Jyun-Ying Lin ,  Alexander Kalnitsky ,  Shih-Fen Huang ,  Shu-Hui Su ,  Ting-Chen Hsu ,  Tuo-Hsin Chien ,  Felix Ying-Kit Tsui ,  Shi-Min Wu ,  Yu-Chi Chang

IPC: H01L29/94 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/764 ,  H01L23/00 ,  H01L29/66 ,  H01L49/02

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a capacitor over a substrate. The capacitor includes a plurality of conductive layers and a plurality of dielectric layers. The plurality of conductive layers and dielectric layers define a base structure and a first protrusion structure extending downward from the base structure towards a bottom surface of the substrate. The first protrusion structure comprises one or more surfaces defining a first cavity. A top of the first cavity is disposed below the base structure.

公开(公告)号：US12166067B2

公开(公告)日：2024-12-10

申请号：US17729321

申请日：2022-04-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Yuan Shih ,  Kai-Fung Chang ,  Shih-Fen Huang ,  Yan-Jie Liao

IPC: H01L29/00 ,  H01L49/02

Abstract: In some embodiments, the present disclosure relates to a method of forming a metal-insulator-metal (MIM) device. The method may be performed by depositing a bottom electrode layer over a substrate, depositing a dielectric layer over the bottom electrode layer, depositing a top electrode layer over the dielectric layer, and depositing a first titanium getter layer over the top electrode layer. The first titanium getter layer, the top electrode layer, and the dielectric layer are patterned to expose a peripheral portion of the bottom electrode layer. A passivation layer is deposited over the substrate, the first titanium getter layer, and the peripheral portion of the bottom electrode layer.

公开(公告)号：US20240397828A1

公开(公告)日：2024-11-28

申请号：US18321268

申请日：2023-05-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ching-Hui Lin ,  Yi-Hsien Chang ,  Chun-Ren Cheng ,  Shih-Fen Huang ,  Fu-Chun Huang ,  Chao-Hung Chu ,  Po-Chen Yeh

IPC: H10N30/87 ,  H10N30/057 ,  H10N30/063 ,  H10N30/072 ,  H10N30/50

Abstract: Various embodiments of the present disclosure are directed towards a piezoelectric device including a piezoelectric structure over a substrate. A first conductive structure is disposed on a lower surface of the piezoelectric structure. The first conductive structure includes one or more first movable elements directly contacting the piezoelectric structure. A second conductive structure is disposed on an upper surface of the piezoelectric structure. The second conductive structure includes one or more second movable elements directly contacting the piezoelectric structure. The one or more second movable elements directly overlie the one or more first movable elements.

公开(公告)号：US12082505B2

公开(公告)日：2024-09-03

申请号：US17881934

申请日：2022-08-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Alexander Kalnitsky ,  Chun-Ren Cheng ,  Chi-Yuan Shih ,  Kai-Fung Chang ,  Shih-Fen Huang ,  Yi-Chuan Teng ,  Yi Heng Tsai ,  You-Ru Lin ,  Yan-Jie Liao

IPC: H10N30/04 ,  G01N25/58 ,  H10N30/00 ,  H10N30/067 ,  H10N30/87 ,  H10N30/063

CPC classification number: H10N30/10513 ,  G01N25/58 ,  H10N30/04 ,  H10N30/067 ,  H10N30/877 ,  H10N30/063

Abstract: In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.