公开(公告)号：US11710764B2

公开(公告)日：2023-07-25

申请号：US16020131

申请日：2018-06-27

Applicant: Texas Instruments Incorporated

Inventor： Poornika Fernandes ,  Sagnik Dey ,  Luigi Colombo ,  Haowen Bu ,  Scott Robert Summerfelt ,  Mark Robert Visokay ,  John Paul Campbell

IPC: H01L21/285 ,  H01L49/02 ,  H01L21/3213 ,  H01L21/306

CPC classification number: H01L28/91 ,  H01L21/28518 ,  H01L21/306 ,  H01L21/32133

Abstract: An integrated circuit (IC) including a semiconductor surface layer of a substrate including functional circuitry having circuit elements formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal capacitor (MIM) capacitor on the semiconductor surface layer for realizing at least one circuit function. The MIM capacitor includes a multilevel bottom capacitor plate having an upper top surface, a lower top surface, and sidewall surfaces that connect the upper and lower top surfaces (e.g., a bottom plate layer on a three-dimensional (3D) layer or the bottom capacitor plate being a 3D bottom capacitor plate). At least one capacitor dielectric layer is on the bottom capacitor plate. A top capacitor plate is on the capacitor dielectric layer, and there are contacts through a pre-metal dielectric layer to contact the top capacitor plate and the bottom capacitor plate.

公开(公告)号：US20210202688A1

公开(公告)日：2021-07-01

申请号：US17181485

申请日：2021-02-22

Applicant: Texas Instruments Incorporated

Inventor： Poornika Fernandes ,  Luigi Colombo ,  Haowen Bu

IPC: H01L49/02 ,  H01L21/02 ,  H01L27/06 ,  H01G4/08 ,  H01L29/06

Abstract: In a described example, an integrated circuit includes a capacitor first plate; a dielectric stack over the capacitor first plate comprising silicon nitride and silicon dioxide with a capacitance quadratic voltage coefficient less than 0.5 ppm/V2; and a capacitor second plate over the dielectric stack.

公开(公告)号：US10068771B2

公开(公告)日：2018-09-04

申请号：US15865758

申请日：2018-01-09

Applicant: Texas Instruments Incorporated

Inventor： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

IPC: H01L21/00 ,  H01J37/00 ,  H01L21/28 ,  C23C16/455 ,  C23C16/458 ,  H01J37/32 ,  H01L21/02 ,  H01L29/51

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

公开(公告)号：US09337046B1

公开(公告)日：2016-05-10

申请号：US15003466

申请日：2016-01-21

Applicant: Texas Instruments Incorporated

Inventor： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

IPC: H01L21/28 ,  H01L29/51

CPC classification number: H01L21/28158 ,  C23C16/45557 ,  C23C16/4582 ,  H01J37/32752 ,  H01J37/32825 ,  H01J37/32899 ,  H01J2237/3321 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/3105 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/6776 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

公开(公告)号：US11670671B2

公开(公告)日：2023-06-06

申请号：US17181485

申请日：2021-02-22

Applicant: Texas Instruments Incorporated

Inventor： Poornika Fernandes ,  Luigi Colombo ,  Haowen Bu

IPC: H01L21/02 ,  H01L49/02 ,  H01L27/06 ,  H01G4/08 ,  H01L29/06

CPC classification number: H01L28/40 ,  H01G4/085 ,  H01L21/022 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L27/0629 ,  H01L29/0649

Abstract: In a described example, an integrated circuit includes a capacitor first plate; a dielectric stack over the capacitor first plate comprising silicon nitride and silicon dioxide with a capacitance quadratic voltage coefficient less than 0.5 ppm/V2; and a capacitor second plate over the dielectric stack.

公开(公告)号：US20220375856A1

公开(公告)日：2022-11-24

申请号：US17489910

申请日：2021-09-30

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Yuguo Wang ,  Haowen Bu

IPC: H01L23/522 ,  H01L23/525 ,  H01L21/70 ,  H01L21/283

Abstract: A method and an electronic device that includes an isolation structure having a dielectric material on or in a semiconductor surface layer, and a passive circuit component having a metal silicide structure on a side of the isolation structure, there the metal silicide structure includes a metal silicide portion and a dielectric portion, the dielectric portion of the metal silicide structure including one of silicon nitride, silicon oxide, silicon carbide, silicon carbon nitride, and silicon oxynitride. The method includes forming a dielectric material of the isolation structure on or in the semiconductor surface layer, forming a silicon-rich dielectric layer on a side of the isolation structure, and siliciding the silicon-rich dielectric layer to form the metal silicide structure on the side of the isolation structure.

公开(公告)号：US10964778B2

公开(公告)日：2021-03-30

申请号：US15902764

申请日：2018-02-22

Applicant: Texas Instruments Incorporated

Inventor： Poornika Fernandes ,  Luigi Colombo ,  Haowen Bu

IPC: H01L49/02 ,  H01L21/02 ,  H01L27/06 ,  H01G4/08 ,  H01L29/06

Abstract: In a described example, an integrated circuit includes a capacitor first plate; a dielectric stack over the capacitor first plate comprising silicon nitride and silicon dioxide with a capacitance quadratic voltage coefficient less than 0.5 ppm/V2; and a capacitor second plate over the dielectric stack.

公开(公告)号：US20200219969A1

公开(公告)日：2020-07-09

申请号：US16820549

申请日：2020-03-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika Fernandes ,  Luigi Colombo ,  Haowen Bu

IPC: H01L49/02 ,  C23C16/455 ,  H01L21/677 ,  H01G4/018

Abstract: In a described example, a method for forming a capacitor includes: forming a capacitor first plate over a non-conductive substrate; flowing ammonia and nitrogen gas into a plasma enhanced chemical vapor deposition (PECVD) chamber containing the non-conductive substrate; stabilizing a pressure and a temperature in the PECVD chamber; turning on radio frequency high frequency (RF-HF) power to the PECVD chamber; pretreating the capacitor first plate for at least 60 seconds; depositing a capacitor dielectric on the capacitor first plate; and depositing a capacitor second plate on the capacitor dielectric.

公开(公告)号：US09779946B2

公开(公告)日：2017-10-03

申请号：US15404561

申请日：2017-01-12

Applicant: Texas Instruments Incorporated

Inventor： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

IPC: H01J37/00 ,  H01L21/00 ,  H01L21/28 ,  H01L21/67

CPC classification number: H01L21/28158 ,  C23C16/45557 ,  C23C16/4582 ,  H01J37/32752 ,  H01J37/32825 ,  H01J37/32899 ,  H01J2237/3321 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/3105 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/6776 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

公开(公告)号：US09576804B2

公开(公告)日：2017-02-21

申请号：US15180481

申请日：2016-06-13

Applicant: Texas Instruments Incorporated

Inventor： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

IPC: H01J37/00 ,  H01L21/00 ,  H01L21/28 ,  H01L21/02 ,  H01L21/67 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/28158 ,  C23C16/45557 ,  C23C16/4582 ,  H01J37/32752 ,  H01J37/32825 ,  H01J37/32899 ,  H01J2237/3321 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/3105 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/6776 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

Abstract translation: 可以减少在制造栅极电介质结构中使用的工艺之间发生的栅极介电层的氧化物生长。 氧化物生长的减少可以通过将栅极电介质层保持在有效的方式来实现，以在制造栅极电介质结构中的至少两个顺序的工艺步骤之间减轻栅极电介质层的氧化物生长。 维持栅极电介质层在有效减少氧化物生长的环境中也改善了注入栅电介质的氮的均匀性。