公开(公告)号：US10833103B2

公开(公告)日：2020-11-10

申请号：US16563627

申请日：2019-09-06

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Haruka Sakuma ,  Hidenori Miyagawa ,  Shosuke Fujii ,  Kiwamu Sakuma ,  Fumitaka Arai

IPC: G11C11/22 ,  H01L27/11597 ,  H01L29/51 ,  G11C16/04 ,  G11C16/10 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/528 ,  H01L21/28 ,  H01L21/02 ,  H01L21/311 ,  H01L21/306

Abstract: A semiconductor memory device includes: a substrate; a plurality of first semiconductor portions arranged in a first direction intersecting a surface of the substrate; a first gate electrode extending in the first direction, the first gate electrode facing the plurality of first semiconductor portions from a second direction intersecting the first direction; a first insulating portion provided between the first semiconductor portions and the first gate electrode; a first wiring separated from the first gate electrode in the first direction; a second semiconductor portion connected to one end in the first direction of the first gate electrode and to the first wiring; a second gate electrode facing the second semiconductor portion; and a second insulating portion provided between the second semiconductor portion and the second gate electrode.

公开(公告)号：US10008509B2

公开(公告)日：2018-06-26

申请号：US15648149

申请日：2017-07-12

Applicant: Toshiba Memory Corporation

Inventor： Haruka Sakuma ,  Kiwamu Sakuma ,  Masahiro Kiyotoshi

IPC: H01L27/1157 ,  H01L29/66 ,  H01L29/792 ,  H01L29/423 ,  H01L27/11578 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L27/1157 ,  B82Y10/00 ,  H01L27/11578 ,  H01L29/0673 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/792

Abstract: Stack structures are arranged in a first direction horizontal to a semiconductor substrate, one of which has a longitudinal direction along a second direction. One stack structure has a plurality of semiconductor layers stacked between interlayer insulating layers. A memory film is formed on side surfaces of the stack structures and include a charge accumulation film of the memory cell. Conductive films are formed on side surfaces of the stack structures via the memory film. One stack structure has a shape increasing in width from above to below in a cross-section including the first and third directions. One conductive film has a shape increasing in width from above to below in a cross-section including the second and third directions. Predetermined portions in the semiconductor layers have different impurity concentrations between upper and lower semiconductor layers.

公开(公告)号：US10446552B2

公开(公告)日：2019-10-15

申请号：US15912664

申请日：2018-03-06

Applicant: Toshiba Memory Corporation

Inventor： Dandan Zhao ,  Reika Ichihara ,  Haruka Sakuma ,  Yuuichiro Mitani

IPC: H01L27/10 ,  G11C13/00 ,  H01L27/105 ,  H01L45/00

Abstract: According to one embodiment, a memory element includes a first conductive layer, a second conductive layer, and a first layer. The first conductive layer includes an ion source. The first layer includes a first element and is provided between the first conductive layer and the second conductive layer. An electronegativity of the first element is greater than 2. The first layer includes a first region and a second region. The first region includes the first element. The second region is provided between the first region and the second conductive layer. The second region does not include the first element, or the second region includes the first element, and a concentration of the first element in the first region is higher than a concentration of the first element in the second region.