中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

20 records (took 0.016 seconds)

    Memory device
    2.
    发明授权
    Memory device 有权

    公开(公告)号：US09997569B2

    公开(公告)日：2018-06-12

    申请号：US15227053

    申请日：2016-08-03

    Applicant: Toshiba Memory Corporation

    Inventor： Marina Yamaguchi ,  Shosuke Fujii ,  Yuuichi Kamimuta ,  Takayuki Ishikawa ,  Masumi Saitoh

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/249 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/145

    Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode, a first layer, and a second layer. The first electrode includes a first element. The first layer is provided between the first electrode and the second electrode. The first layer includes at least one of an insulator or a first semiconductor. The second layer is provided between the first layer and the second electrode. The second layer includes a first region and a second region. The second region is provided between the first region and the second electrode. The second region includes a second element. A standard electrode potential of the second element is lower than a standard electrode potential of the first element. A concentration of nitrogen in the first region is higher than a concentration of nitrogen in the second region.

    Memory element
    4.
    发明授权
    Memory element 有权

    公开(公告)号：US10249818B1

    公开(公告)日：2019-04-02

    申请号：US15912613

    申请日：2018-03-06

    Applicant: Toshiba Memory Corporation

    Inventor： Marina Yamaguchi ,  Shosuke Fujii ,  Riichiro Takaishi ,  Yuuichi Kamimuta ,  Shoichi Kabuyanagi ,  Masumi Saitoh

    IPC: H01L45/00 ,  H01L27/24 ,  G11C11/22 ,  H01L49/02

    Abstract: According to one embodiment, a memory element includes a first layer, a second layer, and a third layer. The first layer is conductive. The second layer is conductive. The third layer includes hafnium oxide and is provided between the first layer and the second layer. The first layer includes a first region, a second region, and a third region. The first region includes a first element and a first metallic element. The first element is selected from a group consisting of carbon and nitrogen. The second region includes a second metallic element and is provided between the first region and the third layer. The third region includes titanium oxide and is provided between the second region and the third layer.

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US10916654B2

    公开(公告)日：2021-02-09

    申请号：US16549540

    申请日：2019-08-23

    Applicant: Toshiba Memory Corporation

    Inventor： Shosuke Fujii

    IPC: H01L29/78 ,  H01L27/11 ,  G11C5/06 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11556 ,  G11C11/22 ,  H01L27/11585

    Abstract: The semiconductor memory device of the embodiment includes a stacked body including interlayer insulating layers and gate electrode layers alternately stacked in a first direction; a semiconductor layer provided in the stacked body and extending in the first direction; a first insulating layer provided between the semiconductor layer and the gate electrode layers; conductive layers provided between the first insulating layer and the gate electrode layers; and second insulating layers provided between the conductive layers and the gate electrode layers and the second insulating layers containing ferroelectrics. Two of the conductive layers adjacent to each other in the first direction are separated by one of the interlayer insulating layers interposed between the two of the conductive layers, and a first thickness of one of the gate electrode layers in the first direction is smaller than a second thickness of one of the conductive layers in the first direction.

    Semiconductor memory device
    7.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US10784312B1

    公开(公告)日：2020-09-22

    申请号：US16564667

    申请日：2019-09-09

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Shoichi Kabuyanagi ,  Shosuke Fujii ,  Masumi Saitoh

    IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00

    Abstract: A semiconductor memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction, a variable resistance film provided between these, a third wiring extending in a third direction, a first semiconductor section connected to the first wiring and the third wiring, a first gate electrode facing the first semiconductor section, a contact connected to the second wiring, a fourth wiring further from the substrate than the contact is, a second semiconductor section connected to the contact and the fourth wiring, and a second gate electrode facing the second semiconductor section. The first semiconductor section, the first gate electrode, the second semiconductor section, and the second gate electrode respectively include a portion included in a cross section extending in the second direction and the third direction.

    Memory device
    8.
    发明授权
    Memory device 有权

    公开(公告)号：US10153326B2

    公开(公告)日：2018-12-11

    申请号：US14958309

    申请日：2015-12-03

    Applicant: Toshiba Memory Corporation

    Inventor： Masato Koyama ,  Harumi Seki ,  Shosuke Fujii ,  Hidenori Miyagawa

    IPC: H01L45/00 ,  H01L27/24

    Abstract: According to one embodiment, a memory device includes a first conductive layer, a second conductive layer, a first insulating layer and a first layer. The first conductive layer includes a first metal capable of forming a compound with silicon. The second conductive layer includes at least one selected from a group consisting of tungsten, molybdenum, platinum, tungsten nitride, molybdenum nitride, and titanium nitride. The first insulating layer is provided between the first conductive layer and the second conductive layer. The first layer is provided between the first insulating layer and the second conductive layer. The first layer includes silicon.

Patent Agency Ranking