公开(公告)号：US20190287993A1

公开(公告)日：2019-09-19

申请号：US16118356

申请日：2018-08-30

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Masaki KONDO

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L21/768 ,  G11C16/10

Abstract: A semiconductor memory device includes a semiconductor substrate, a pillar disposed above the semiconductor substrate and extending in a first direction crossing a principal surface of the semiconductor substrate, a plurality of first memory cells arranged on a first side surface of the pillar along the first direction, and a plurality of second memory cells arranged on a second side surface of the pillar along the first direction. The memory device further includes a plurality of first control gate layers respectively connected to the first memory cells, a plurality of second control gate layers respectively connected to the second memory cells, and a stacked film disposed between one of the first control gate layers and one of the second control gate layers, the stacked film including a first insulating layer, a second insulating layer, and an electron capture layer disposed between the first insulating layer and the second insulating layer.

公开(公告)号：US20200294554A1

公开(公告)日：2020-09-17

申请号：US16557475

申请日：2019-08-30

Applicant: Toshiba Memory Corporation

Inventor： Takayuki KAKEGAWA ,  Shinya NAITO ,  Masaki KONDO ,  Takashi KURUSU ,  Hiroshi TAKEDA ,  Nayuta KARIYA

IPC: G11C5/06 ,  H01L27/11556 ,  H01L27/11524

Abstract: A semiconductor memory device according to an embodiment includes a substrate, first and second conductive layers, and a first pillar. The first conductive layer is provided above the substrate and includes a first N-type semiconductor region and a first P-type semiconductor region. The second conductive layers are provided above the first conductive layer and stacked at intervals. The first pillar includes a first semiconductor layer and a first insulating layer. The first semiconductor layer is provided through the second conductive layers and is in contact with each of the first N-type semiconductor region and the first P-type semiconductor region. The first insulating layer is provided between the first semiconductor layer and the second conductive layers.

公开(公告)号：US20200303400A1

公开(公告)日：2020-09-24

申请号：US16502877

申请日：2019-07-03

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Fumitaka ARAI ,  Masakazu GOTO ,  Masaki KONDO ,  Keiji HOSOTANI ,  Nobuyuki MOMO

IPC: H01L27/11582 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  H01L27/1157 ,  H01L27/11573

Abstract: According to one embodiment, a semiconductor memory device includes: a first interconnecting layer; a first signal line; a first memory cell that stores first information between the first interconnecting layer and the first signal line; second to fourth interconnecting layers provided above the first interconnecting layer; fifth to seventh interconnecting layers disposed apart from the second to fourth interconnecting layers; a second signal line coupled to the first signal line; a third signal line coupled to the first and second signal lines and the sixth interconnecting layer; and, first to fifth transistors.

公开(公告)号：US20200091174A1

公开(公告)日：2020-03-19

申请号：US16283627

申请日：2019-02-22

Applicant: Toshiba Memory Corporation

Inventor： Tomoya SANUKI ,  Yusuke HIGASHI ,  Hideto HORII ,  Masaki KONDO ,  Hiroki TOKUHIRA ,  Hideaki AOCHI

IPC: H01L27/11582 ,  H01L27/1157 ,  G11C16/04 ,  G11C16/26 ,  G11C16/16

Abstract: An example semiconductor device includes: n conductive layers including first to nth conductive layers stacked in a first direction; a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type closer to the nth conductive layer than the first semiconductor region; a semiconductor layer provided between the first semiconductor region and the second semiconductor region, extending in the first direction, penetrating the n conductive layers, and having an impurity concentration lower than a first conductive impurity concentration of the first region and a second conductive impurity concentration of the second region; n charge storage regions including first to nth charge storage regions provided between the n conductive layers and the semiconductor layer, and a control circuit that controls a voltage applied to the n conductive layers to always prevent charges from being stored in at least one of the n charge storage regions.

公开(公告)号：US20200090751A1

公开(公告)日：2020-03-19

申请号：US16692374

申请日：2019-11-22

Applicant: Toshiba Memory Corporation

Inventor： Takashi KOBAYASHI ,  Yoichi MINEMURA ,  Eietsu TAKAHASHI ,  Masaki KONDO ,  Daisuke HAGISHIMA

IPC: G11C16/04 ,  G11C16/32 ,  G11C16/10 ,  G11C11/56 ,  H01L27/11529 ,  G06F3/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/28 ,  G11C16/24

Abstract: According to one embodiment, a semiconductor memory device includes: a memory string including first and second select transistors and memory cell transistors; a bit line connected to the first select transistor; word lines which are connected to gates of the memory cell transistors, respectively; first and second select gate lines which are connected to gates of the first and second select transistors, respectively; a first contact plug connected to the first select gate line; a first wiring layer provided on the first contact plug; a second contact plug connected to the second select gate line; a second wiring layer provided on the second contact plug; and a row decoder connected to the first and second wiring layers. The row decoder applies different voltages to the first select gate line and the second select gate line.