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公开(公告)号：US08477528B2
公开(公告)日：2013-07-02
申请号：US12443349
申请日：2007-09-25
IPC分类号： G11C11/00
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1675 , H01L43/08
摘要： A magnetic memory cell 1 is provided with a magnetic recording layer 10 which is a ferromagnetic layer and a pinned layer 30 connected with the magnetic recording layer 10 through a non-magnetic layer 20. The magnetic recording layer 10 has a magnetization inversion region 13, a first magnetization fixed region 11 and a second magnetization fixed region 12. The magnetization inversion region 13 has a magnetization whose orientation is invertible and overlaps the pinned layer 30. The first magnetization fixed region 11 is connected with a first boundary B1 in the magnetization inversion region 13 and a magnetization orientation is fixed on a first direction. The second magnetization fixed region 12 is connected with a second boundary B2 in magnetization inversion region 13 and a magnetization orientation is fixed on a second direction. The first direction and the second direction are opposite to each other.
摘要翻译： 磁存储单元1设置有磁记录层10，磁记录层10是铁磁层，和通过非磁性层20与磁记录层10连接的钉扎层30.磁记录层10具有磁化反转区域13， 第一磁化固定区域11和第二磁化固定区域12.磁化反转区域13具有其取向可反转并与被钉扎层30重叠的磁化。第一磁化固定区域11与磁化反转中的第一边界B1连接 区域13和磁化取向在第一方向固定。 第二磁化固定区域12与磁化反转区域13中的第二边界B2连接，并且磁化取向固定在第二方向上。 第一方向和第二方向彼此相反。
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公开(公告)号：US07916520B2
公开(公告)日：2011-03-29
申请号：US11574121
申请日：2005-08-19
IPC分类号： G11C11/00
CPC分类号： H01L27/228 , G11C11/15 , H01L43/08 , Y10S977/935
摘要： A memory cell is used which includes a plurality of magneto-resistive elements and a plurality of laminated ferrimagnetic structure substances. The plurality of the magneto-resistive elements are placed corresponding to respective positions where a plurality of first wirings extended in a first direction intersects with a plurality of second wirings extended in a second direction which is substantially perpendicular to the first direction. The plurality of the laminated ferrimagnetic structure substances corresponds to the plurality of the magneto-resistive elements, respectively, is placed to have a distance of a predetermined range from the respective plurality of the magneto-resistive elements, and has a laminated ferrimagnetic structure. The magneto-resistive element includes a free layer having a laminated ferrimagnetic structure, a fixed layer, and a nonmagnetic layer interposed between the free layer and the fixed layer.
摘要翻译： 使用包括多个磁阻元件和多个叠层铁磁结构物质的存储单元。 多个磁阻元件对应于在第一方向上延伸的多个第一布线与基本上垂直于第一方向的第二方向延伸的多个第二布线相对应的相应位置放置。 多个叠层铁氧体结构物质分别对应于多个磁阻元件，放置成距离相应的多个磁阻元件具有预定范围的距离，并具有叠层铁磁结构。 磁阻元件包括层叠的铁磁结构，固定层和插入在自由层和固定层之间的非磁性层的自由层。
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3.发明授权Resistance change semiconductor memory device and method of reading data with a first and second switch circuit 有权电阻变化半导体存储器件以及利用第一和第二开关电路读取数据的方法公开(公告)号：US07885131B2
公开(公告)日：2011-02-08
申请号：US11815325
申请日：2006-02-01
IPC分类号： G11C7/02
CPC分类号： G11C11/16 , G11C7/02 , G11C7/062 , G11C7/14 , G11C11/4091 , G11C11/4099 , G11C13/0002 , G11C13/0004 , G11C13/004 , G11C2013/0054
摘要： A semiconductor memory device of the present invention comprises a memory array and a read circuit that reads data of a selected cell. The memory array includes a plurality of memory cells and a reference cell each having a memory element that stores data based on change in resistance value. The read circuit includes: a voltage comparison unit that compares a value corresponding to a sense current from the selected cell with a value corresponding to a reference current from the reference cell; a first switch; and a second switch. Both of the first and second switches are provided at a subsequent stage of a decoder and at a preceding stage of the voltage comparison unit. The second switch circuit controls input of the value corresponding to the sense current to the voltage comparison unit, while the first switch circuit controls input of the value corresponding to the reference current to the voltage comparison unit.
摘要翻译： 本发明的半导体存储器件包括存储器阵列和读取所选择的单元的数据的读取电路。 存储器阵列包括多个存储器单元和参考单元，每个存储器单元具有存储元件，该存储元件基于电阻值的变化存储数据。 读取电路包括：电压比较单元，将来自所选择的单元的检测电流的值与来自参考单元的参考电流对应的值进行比较; 第一个开关 和第二开关。 第一和第二开关都被提供在解码器的后续阶段，并且在电压比较单元的前一级提供。 第二开关电路将对应于感测电流的值的输入控制到电压比较单元，而第一开关电路将对应于参考电流的值的输入控制到电压比较单元。
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公开(公告)号：US07885095B2
公开(公告)日：2011-02-08
申请号：US12303821
申请日：2007-06-01
CPC分类号： G11C11/1673 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1675 , H01L27/228
摘要： A magnetic random access memory of the present invention includes: a plurality of first wirings and a plurality of second wirings extending in a first direction; a plurality of third wirings and a plurality of fourth wirings extending in a second direction; and a plurality of memory cells provided at intersections of the plurality of first wirings and the plurality of third wirings, respectively. Each of the plurality of memory cells includes: a first transistor and a second transistor connected in series between one of the plurality of first wirings and one of the plurality of second wirings and controlled in response to a signal on one of the plurality of third wirings, a first magnetic resistance element having one end connected to a write wiring through which the first transistor and the second transistor are connected, and the other end grounded; and a second magnetic resistance element having one end connected to the write wiring, and the other end connected to the fourth wiring.
摘要翻译： 本发明的磁性随机存取存储器包括：沿第一方向延伸的多个第一布线和多条第二布线; 多个第三布线和沿第二方向延伸的多个第四布线; 以及多个存储单元，分别设置在所述多个第一布线和所述多个第三布线的交点处。 所述多个存储单元中的每一个包括：第一晶体管和第二晶体管，其串联连接在所述多个第一布线中的一个与所述多个第二布线中的一个之间，并响应于所述多个第三布线之一上的信号而被控制 第一磁阻元件，其一端连接到第一晶体管和第二晶体管连接的写入布线，另一端接地; 以及第二磁阻元件，其一端连接到写入布线，另一端连接到第四布线。
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公开(公告)号：US07764552B2
公开(公告)日：2010-07-27
申请号：US12085158
申请日：2006-11-07
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C11/1675 , G11C11/1693 , G11C11/1697 , Y10T307/826
摘要： A semiconductor integrated circuit is provided that can prevent an internal voltage from the voltage generating circuit from varying during a long term. The semiconductor integrated circuit of the present invention includes a voltage generating circuit configured to generate a reference voltage; a function circuit configured to operate by using the reference voltage; a first capacitance connected to a first node between the voltage generating circuit and the function circuit; and a switch provided between the voltage generating circuit and the first node. The switch is in a turned-off state at least for a period during which the function circuit is in an activated state.
摘要翻译： 提供一种可以防止来自电压产生电路的内部电压在长期内变化的半导体集成电路。 本发明的半导体集成电路包括：电压产生电路，被配置为产生参考电压; 功能电路，被配置为通过使用所述参考电压进行操作; 连接到所述电压产生电路和所述功能电路之间的第一节点的第一电容; 以及设置在电压产生电路和第一节点之间的开关。 至少在功能电路处于激活状态的期间，开关处于截止状态。
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6.发明申请Magnetic random access memory and operating method of magnetic random access memory 有权磁随机存取存储器和磁随机存取存储器的操作方法公开(公告)号：US20090262571A1
公开(公告)日：2009-10-22
申请号：US12308062
申请日：2007-06-01
IPC分类号： G11C11/00 , G11C11/14 , G11C11/416
CPC分类号： G11C11/1659 , G11C11/1655 , G11C11/1675
摘要： A magnetic random access memory includes: a first and second wirings, a plurality of third wirings, a plurality of memory cells and a terminating unit. The first and second wirings extend in a Y direction. The plurality of third wirings extends in an X direction. The memory cell is provided correspondingly to an intersection between the first and second wirings and the third wiring. The terminating unit is provided between the plurality of memory cells and connected to the first and second wirings. The memory cell includes transistors and a magnetoresistive element. The transistors are connected in series between the first and second wirings and controlled based on a signal of the third wiring. The magnetoresistive element is connected to a wiring through which the transistors are connected. At a time of a writing operation, when the write current Iw is supplied from one of the first and second wiring to the other through the transistors, the terminating unit grounds the other.
摘要翻译： 磁性随机存取存储器包括：第一和第二布线，多个第三布线，多个存储单元和终端单元。 第一和第二布线沿Y方向延伸。 多个第三配线沿X方向延伸。 对应于第一和第二布线和第三布线之间的交叉点设置存储单元。 终端单元设置在多个存储单元之间并连接到第一和第二布线。 存储单元包括晶体管和磁阻元件。 晶体管串联连接在第一和第二布线之间，并根据第三布线的信号进行控制。 磁阻元件连接到晶体管连接到的布线。 在写入操作时，当写入电流Iw通过晶体管从第一和第二布线中的一个提供给另一个时，端接单元接地。
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公开(公告)号：US20060158945A1
公开(公告)日：2006-07-20
申请号：US11384920
申请日：2006-03-20
IPC分类号： G11C7/00
CPC分类号： G11C13/004 , G11C7/06 , G11C11/16 , G11C11/1673 , G11C13/0061 , G11C2013/0047 , G11C2013/0054 , G11C2013/0057 , G11C2207/066
摘要： By first readout, the current input from a selected cell 13 is converted by a preamplifier 3 and a VCO 4 into pulses of a frequency inversely proportionate to the current value, and the number of the pulses within a preset time interval is counted by a counter 5 so as to be stored in a readout value register 6. A selected cell is then written to one of two storage states, and second readout is then carried out. The storage state of the selected cell is verified by comparing a count value of the counter for the second readout, a count value for the first readout as stored in a readout value register and a reference value stored in a reference value register 7 to one another. By the use of the VCO, the integrating capacitor for the current or reference pulse generating means, so far needed, may be eliminated to assure a small area, low power consumption and fast readout.
摘要翻译： 通过第一读出，来自所选单元13的当前输入由前置放大器3和VCO4转换为与当前值成反比的频率的脉冲，并且预设时间间隔内的脉冲数由计数器计数 以便存储在读出值寄存器6中。 然后将选定的单元写入两个存储状态之一，然后执行第二次读出。 通过将存储在读出值寄存器中的第一次读出的计数值和存储在参考值寄存器7中的参考值彼此进行比较来验证所选单元的存储状态 。 通过使用VCO，可以消除目前需要的电流或参考脉冲发生装置的积分电容器，以确保小面积，低功耗和快速读出。
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公开(公告)号：US06990015B2
公开(公告)日：2006-01-24
申请号：US10329463
申请日：2002-12-27
IPC分类号： G11C11/15
摘要： A semiconductor memory device which uses tunneling magnetoresistive element as memory cells and eliminates the temperature dependencies in a write margin and read margin in such a way as to be able to accurately output a write current at the time of writing the memory cells. The semiconductor memory device is constructed in such a way that main bit lines or main word lines are laid out so as to cross bit lines or word lines perpendicularly, and a main bit line selector or a main word line selector which respectively selects the main bit line or the main word line is arranged outside a memory cell array.
摘要翻译： 一种半导体存储器件，其使用隧道磁阻元件作为存储器单元，并且以这样的方式消除写入裕度和读取裕度中的温度依赖性，使得能够在写入存储器单元时精确地输出写入电流。 半导体存储器件被构造成使得主位线或主字线布置成垂直于位线或字线交叉，主位线选择器或主字选择器分别选择主位 线或主字线布置在存储单元阵列的外部。
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公开(公告)号：US07948783B2
公开(公告)日：2011-05-24
申请号：US12515898
申请日：2007-11-12
IPC分类号： G11C15/02
CPC分类号： H01L27/228 , B82Y10/00 , B82Y25/00 , G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , H01F10/3254 , H01F10/3272 , H01L43/08
摘要： An MRAM comprises: a plurality of magnetic memory cells each having a magnetoresistive element; and a magnetic field application section. The magnetic field application section applies an offset adjustment magnetic field in a certain direction to the plurality of magnetic memory cells from outside the plurality of magnetic memory cells. Respective data stored in the plurality of magnetic memory cells become the same when the offset adjustment magnetic field is removed.
摘要翻译： MRAM包括：多个具有磁阻元件的磁存储单元; 和磁场施加部。 磁场施加部从多个磁存储单元的外部向多个磁存储单元施加一定方向的偏移调整磁场。 当去除偏移调整磁场时，存储在多个磁存储单元中的各个数据变得相同。
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公开(公告)号：US07813164B2
公开(公告)日：2010-10-12
申请号：US11661205
申请日：2005-08-26
IPC分类号： G11C11/00
CPC分类号： G11C11/15 , H01L27/228 , H01L43/08
摘要： A magneto-resistance element includes a free layer, a fixed layer and a non-magnetic layer interposed between the free layer and the fixed layer. The free layer has a first magnetic layer, a second magnetic layer, a third magnetic layer, a first non-magnetic layer interposed between the first magnetic layer and the second magnetic layer, and a second non-magnetic layer interposed between the second magnetic layer and the third magnetic layer. The first magnetic layer, the second magnetic layer and the third magnetic layer are coupled such that spontaneous magnetizations have a helical structure.
摘要翻译： 磁阻元件包括位于自由层和固定层之间的自由层，固定层和非磁性层。 自由层具有第一磁性层，第二磁性层，第三磁性层，介于第一磁性层和第二磁性层之间的第一非磁性层，以及介于第二磁性层之间的第二非磁性层 和第三磁性层。 第一磁性层，第二磁性层和第三磁性层被耦合，使得自发磁化具有螺旋结构。
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