利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

11 条记录 (耗时 0.023 秒)

    Oxide film filled structure, oxide film filling method, semiconductor device and manufacturing method thereof
    6.
    发明申请
    Oxide film filled structure, oxide film filling method, semiconductor device and manufacturing method thereof 审中-公开
    氧化膜填充结构，氧化膜填充方法，半导体器件及其制造方法

    公开(公告)号：US20070049046A1

    公开(公告)日：2007-03-01

    申请号：US11502402

    申请日：2006-08-11

    申请人： Mahito Sawada ,  Koyu Asai ,  Yoshihiro Miyagawa ,  Tatsunori Murata

    发明人： Mahito Sawada ,  Koyu Asai ,  Yoshihiro Miyagawa ,  Tatsunori Murata

    IPC分类号： H01L21/31

    CPC分类号： H01L21/31612 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/31662

    摘要： The present invention aims at offering the filled structure of an oxide film etc. which can form an insulating film (oxide film) without void in a predetermined depressed portion by an economical and practical method and without increasing RF bias. According to the first invention, the oxide film filled structure is provided with the foundation (silicon substrate) having a depressed portion (trench), and the oxide film (silicon oxide film) formed in the depressed portion concerned. Here, the oxide film concerned includes the silicon oxide film region of silicon-richness in part at least.

    摘要翻译： 本发明旨在提供一种氧化膜等的填充结构，其可以通过经济实用的方法在不增加RF偏压的情况下在预定凹陷部分中形成无空隙的绝缘膜（氧化膜）。 根据第一发明，氧化膜填充结构设置有具有凹陷部（沟槽）的基底（硅衬底）和形成在所述凹陷部中的氧化膜（氧化硅膜）。 这里，氧化膜至少部分地包括富含硅的氧化硅膜区域。

    Interconnection structure of semiconductor device
    7.
    发明申请
    Interconnection structure of semiconductor device 失效
    半导体器件的互连结构

    公开(公告)号：US20070096322A1

    公开(公告)日：2007-05-03

    申请号：US11635495

    申请日：2006-12-08

    申请人： Koyu Asai ,  Hiroshi Tobimatsu ,  Hiroyuki Kawata ,  Mahito Sawada

    发明人： Koyu Asai ,  Hiroshi Tobimatsu ,  Hiroyuki Kawata ,  Mahito Sawada

    IPC分类号： H01L23/52

    CPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/5226 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnection is provided with a dummy interconnection connected to an interconnection body, and the dummy interconnection is provided with a stress concentration portion in which tensile stress higher than that of the interconnection body is generated. In proximity to the stress concentration portion, an insulating film formed by high-density plasma CVD is provided, and the tensile stress is generated in the stress concentration portion by the insulating film. With this structure, the occurrence of a void can be prevented at any position in the interconnection body.

    摘要翻译： 互连设置有连接到互连体的虚拟互连，并且虚设互连设置有应力集中部，其中产生比互连体高的拉伸应力。 在应力集中部分附近，设置通过高密度等离子体CVD形成的绝缘膜，并且通过绝缘膜在应力集中部分产生拉伸应力。 利用这种结构，可以防止在互连体中的任何位置发生空隙。

    Interconnection structure of semiconductor device
    8.
    发明授权
    Interconnection structure of semiconductor device 失效
    半导体器件的互连结构

    公开(公告)号：US07489040B2

    公开(公告)日：2009-02-10

    申请号：US11635495

    申请日：2006-12-08

    申请人： Koyu Asai ,  Hiroshi Tobimatsu ,  Hiroyuki Kawata ,  Mahito Sawada

    发明人： Koyu Asai ,  Hiroshi Tobimatsu ,  Hiroyuki Kawata ,  Mahito Sawada

    IPC分类号： H01L23/48

    CPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/5226 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnection is provided with a dummy interconnection connected to an interconnection body, and the dummy interconnection is provided with a stress concentration portion in which tensile stress higher than that of the interconnection body is generated. In proximity to the stress concentration portion, an insulating film formed by high-density plasma CVD is provided, and the tensile stress is generated in the stress concentration portion by the insulating film. With this structure, the occurrence of a void can be prevented at any position in the interconnection body.

    摘要翻译： 互连设置有连接到互连体的虚拟互连，并且虚设互连设置有应力集中部，其中产生比互连体高的拉伸应力。 在应力集中部分附近，设置通过高密度等离子体CVD形成的绝缘膜，并且通过绝缘膜在应力集中部分产生拉伸应力。 利用这种结构，可以防止在互连体中的任何位置发生空隙。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    10.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
    半导体器件及其制造方法

    公开(公告)号：US20080014760A1

    公开(公告)日：2008-01-17

    申请号：US11765703

    申请日：2007-06-20

    申请人： Tatsunori MURATA ,  Koyu Asai ,  Hiroaki Iuchi

    发明人： Tatsunori MURATA ,  Koyu Asai ,  Hiroaki Iuchi

    IPC分类号： H01L21/469 ,  H01L29/788

    CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L21/7682 ,  H01L21/76834 ,  H01L27/11521 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14643 ,  H01L27/14689 ,  H01L29/42324

    摘要： When microfabrication is done, a reliable semiconductor device is offered.A semiconductor device has a semiconductor substrate which has a main front surface, a plurality of convex patterns formed on the main front surface of a semiconductor substrate so that each might have a floating gate and a control gate, a first insulating film formed so that the upper surface and the side surface of each of a plurality of convex patterns might be covered, and so that width might become large rather than the portion which covers the lower part side surface of a convex pattern in the portion which covers an upper part side surface, and a second insulating film that covers the upper surface and the side surface of the first insulating film so that the cavity between the adjacent convex patterns may be occluded. The position occluded by the second insulating film of a cavity is a position higher than the upper surface of a floating gate, and is a position lower than the upper surface of a control gate.

    摘要翻译： 当进行微细加工时，提供可靠的半导体器件。 半导体器件具有半导体衬底，该半导体衬底具有主前表面，多个凸形图案形成在半导体衬底的主表面上，以便可以具有浮置栅极和控制栅极，第一绝缘膜形成为使得 可以覆盖多个凸形图案中的每一个的上表面和侧表面，并且使得宽度可能变大，而不是覆盖覆盖上部侧表面的部分中的凸形图案的下部侧表面的部分 以及覆盖第一绝缘膜的上表面和侧表面的第二绝缘膜，使得相邻凸形图案之间的空腔可能被遮挡。 由空腔的第二绝缘膜封闭的位置是比浮动栅极的上表面高的位置，并且是比控制栅极的上表面低的位置。