公开(公告)号：US08467246B2

公开(公告)日：2013-06-18

申请号：US13038962

申请日：2011-03-02

申请人： Tae-Young Kim ,  Young Ho Lim

发明人： Tae-Young Kim ,  Young Ho Lim

IPC分类号： G11C16/06 ,  G11C11/406

CPC分类号： G11C16/16 ,  G11C11/406 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

摘要： A method of operating a non-volatile memory device includes storing one or more addresses of word lines (WLs), but not the entire addresses of the WLs, into a latch, the WLs disposed between a string selection line (SSL) and a ground selection line (GSL), selecting a first WL from the latch, performing an erasing operation on memory cells associated with the string selection line (SSL), the memory cells associated with the SSL constituting a memory block, and verifying the erasing operation on memory cells associated with the selected first WL.

摘要翻译： 一种操作非易失性存储器件的方法包括将一行或多行字线地址（WL）存储在锁存器中，而不是WL的整个地址，布置在串选择线（SSL）和地之间的WL 选择线（GSL），从锁存器中选择第一WL，对与字符串选择行（SSL）相关联的存储单元执行擦除操作，与构成存储器块的SSL相关联的存储器单元，以及验证存储器上的擦除操作 与所选择的第一WL相关联的单元。

公开(公告)号：US20120051138A1

公开(公告)日：2012-03-01

申请号：US13038962

申请日：2011-03-02

申请人： Tae-Young Kim ,  Young Ho Lim

发明人： Tae-Young Kim ,  Young Ho Lim

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/16 ,  G11C11/406 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

摘要： A method of operating a non-volatile memory device includes storing one or more addresses of word lines (WLs), but not the entire addresses of the WLs, into a latch, the WLs disposed between a string selection line (SSL) and a ground selection line (GSL), selecting a first WL from the latch, performing an erasing operation on memory cells associated with the string selection line (SSL), the memory cells associated with the SSL constituting a memory block, and verifying the erasing operation on memory cells associated with the selected first WL.

摘要翻译： 一种操作非易失性存储器件的方法包括将一行或多行字线地址（WL）存储在锁存器中，而不是WL的整个地址，布置在串选择线（SSL）和地之间的WL 选择线（GSL），从锁存器中选择第一WL，对与字符串选择行（SSL）相关联的存储单元执行擦除操作，与构成存储器块的SSL相关联的存储器单元，以及验证存储器上的擦除操作 与所选择的第一WL相关联的单元。

公开(公告)号：US07272049B2

公开(公告)日：2007-09-18

申请号：US11317300

申请日：2005-12-27

申请人： Dong Ku Kang ,  Dae Seok Byeon ,  Young Ho Lim

发明人： Dong Ku Kang ,  Dae Seok Byeon ,  Young Ho Lim

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C8/08 ,  G11C16/08

摘要： A NAND-type nonvolatile semiconductor memory device comprising a cell string that comprises a dummy cell interposed between and connected in series to a string selection transistor and a nonvolatile memory cell is provided. The NAND-type nonvolatile semiconductor memory device further comprises a dummy word line driver adapted to activate a dummy word line to gate the dummy cell.

摘要翻译： 一种NAND型非易失性半导体存储器件，包括一个单元串，该单元串包括插入串联选择晶体管和非易失性存储单元之间并串联连接的虚设单元。 NAND型非易失性半导体存储器件还包括一个虚拟字线驱动器，用于激活伪字线以对虚拟单元进行门极化。

公开(公告)号：US07525850B2

公开(公告)日：2009-04-28

申请号：US11941101

申请日：2007-11-16

申请人： Dong Hyuk Chae ,  Young Ho Lim

发明人： Dong Hyuk Chae ,  Young Ho Lim

IPC分类号： G11C7/10

CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/5642

摘要： A nonvolatile semiconductor memory device is provided which includes a memory array, a page buffer, and a row decoder. The memory array includes a plurality of nonvolatile memory cells, a bit line, and a word line, and the row decoder driven to control the word line of the memory array. The page buffer is electrically connected to the bit line and includes a main data latch and a sub-data latch. The page buffer, which is configured such that flipping of the main data latch is inhibited according to a logic state of the sub-data latch, further includes a main latch block, a sub-latch block, and a latch control block. The main latch block drives the main data latch and maps a logic state of the main data latch to a threshold voltage of a corresponding memory cell through the bit line. The sub-latch block drives the sub-data latch, where the sub-data latch is flipped depending on the voltage level of the bit line. The latch control block selectively flips the main data latch depending on the voltage level of the bit line, where the latch control block is disabled depending on a logic state of the sub-data latch.

摘要翻译： 提供一种包括存储器阵列，页缓冲器和行解码器的非易失性半导体存储器件。 存储器阵列包括多个非易失性存储器单元，位线和字线，并且行解码器被驱动以控制存储器阵列的字线。 页缓冲器电连接到位线，并包括主数据锁存器和子数据锁存器。 根据子数据锁存器的逻辑状态禁止主数据锁存器翻转的页缓冲器还包括主锁存块，子锁存块和锁存控制块。 主锁存块驱动主数据锁存器，并通过位线将主数据锁存器的逻辑状态映射到相应存储器单元的阈值电压。 子锁存块驱动子数据锁存器，其中子数据锁存器根据位线的电压电平翻转。 锁存控制块根据位线的电压电平有选择地翻转主数据锁存器，根据子数据锁存器的逻辑状态，锁存器控制块被禁用。

公开(公告)号：US20060268654A1

公开(公告)日：2006-11-30

申请号：US11416064

申请日：2006-05-03

申请人： Dong Hyuk Chae ,  Young Ho Lim

发明人： Dong Hyuk Chae ,  Young Ho Lim

IPC分类号： G11C8/00

CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/5642

摘要： A nonvolatile semiconductor memory device is provided which includes a memory array, a page buffer, and a row decoder. The memory array includes a plurality of nonvolatile memory cells, a bit line, and a word line, and the row decoder driven to control the word line of the memory array. The page buffer is electrically connected to the bit line and includes a main data latch and a sub-data latch. The page buffer, which is configured such that flipping of the main data latch is inhibited according to a logic state of the sub-data latch, further includes a main latch block, a sub-latch block, and a latch control block. The main latch block drives the main data latch and maps a logic state of the main data latch to a threshold voltage of a corresponding memory cell through the bit line. The sub-latch block drives the sub-data latch, where the sub-data latch is flipped depending on the voltage level of the bit line. The latch control block selectively flips the main data latch depending on the voltage level of the bit line, where the latch control block is disabled depending on a logic state of the sub-data latch.

公开(公告)号：US07480177B2

公开(公告)日：2009-01-20

申请号：US11870528

申请日：2007-10-11

申请人： Sung Soo Lee ,  Young Ho Lim ,  Hyun Chul Cho ,  Dong Hyuk Chae

发明人： Sung Soo Lee ,  Young Ho Lim ,  Hyun Chul Cho ,  Dong Hyuk Chae

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5642

摘要： According to one aspect, a memory cell array includes a bit line connected to a plurality of nonvolatile memory cells, where the nonvolatile memory cells are selectively programmable in any one of at least first, second, third and fourth threshold voltage states, and where the first, second, third and fourth threshold voltage states correspond to four different data values defined by first and second bits. A page buffer circuit stores a logic value as main latch data and is responsive to a main latch signal to selectively flip the logic value of the main latch data according to a voltage level of the bit line. A sub-latch circuit stores a logic value as sub-latch data and is responsive to a sub-latch signal to selectively flip the logic value of the sub-latch data according to the voltage level of the bit line. The memory device is operable in a read mode which reads the threshold voltage state of the non-volatile memory cells and a programming mode which programs the threshold voltage state of the non-volatile memory cells, wherein the page buffer circuit is selectively responsive to the sub-latch data to inhibit flipping of the logic value of the main latch data in the programming mode.

摘要翻译： 根据一个方面，存储单元阵列包括连接到多个非易失性存储单元的位线，其中非易失性存储单元可选择性地以至少第一，第二，第三和第四阈值电压状态中的任何一个编程，并且其中 第一，第二，第三和第四阈值电压状态对应于由第一和第二位定义的四个不同的数据值。 页面缓冲电路将逻辑值存储为主锁存数据，并且响应于主锁存信号，以根据位线的电压电平选择性地翻转主锁存数据的逻辑值。 子锁存电路将逻辑值存储为子锁存数据，并且响应于子锁存信号，以根据位线的电压电平选择性地翻转子锁存数据的逻辑值。 存储器件可读取读取非易失性存储器单元的阈值电压状态的读取模式和编程非易失性存储器单元的阈值电压状态的编程模式，其中页面缓冲器电路有选择地响应于 子锁存数据，以禁止在编程模式下翻转主锁存器数据的逻辑值。

公开(公告)号：US20070076497A1

公开(公告)日：2007-04-05

申请号：US11317303

申请日：2005-12-27

申请人： Dong Hyuk Chae ,  Young Ho Lim

发明人： Dong Hyuk Chae ,  Young Ho Lim

IPC分类号： G11C7/02

CPC分类号： G11C7/1027 ,  G11C29/84

摘要： A burst mode compatible semiconductor memory device having a redundancy memory adapted to repair a normal memory is disclosed. Response margin for a redundancy flag signal and redundancy driving method is improved by sensing generation of an internal address corresponding to an embedded address, and generating a redundancy flag signal, such that the embedded address is an address preceding the address of the memory cell of the normal cell array to be repaired by at least one clock.

公开(公告)号：US20110044105A1

公开(公告)日：2011-02-24

申请号：US12861855

申请日：2010-08-24

申请人： Young Ho Lim ,  Dong Ku Kang ,  Hyeong Jun Kim

发明人： Young Ho Lim ,  Dong Ku Kang ,  Hyeong Jun Kim

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/3418 ,  G11C2211/5648

摘要： A method of programming a non-volatile memory including N-bit multi-level cell (MLC) memory cells includes executing first through (N−1)th page programming operations, using an incremental step pulse programming (ISPP) method, to program first through (N−1)th data pages in the MLC memory cells, where each of the first through (N−1)th page programming operations includes an erase programming of erase cells among the MLC memory cells. The method further includes executing an Nth page programming operation, using the ISPP method, to program an Nth data page in the MLC memory cells.

摘要翻译： 一种编程包括N位多电平单元（MLC）存储器单元的非易失性存储器的方法包括使用增量步进脉冲编程（ISPP）方法执行第一至第（N-1）页编程操作，以首先编程 通过MLC存储器单元中的第（N-1）个数据页，其中第一至第（N-1）页编程操作中的每一个包括MLC存储单元中的擦除单元的擦除编程。 该方法还包括使用ISPP方法执行第N页面编程操作来编程MLC存储器单元中的第N个数据页。

公开(公告)号：US07254076B2

公开(公告)日：2007-08-07

申请号：US11317303

申请日：2005-12-27

申请人： Dong Hyuk Chae ,  Young Ho Lim

发明人： Dong Hyuk Chae ,  Young Ho Lim

IPC分类号： G11C7/02

CPC分类号： G11C7/1027 ,  G11C29/84

摘要： A burst mode compatible semiconductor memory device having a redundancy memory adapted to repair a normal memory is disclosed. Response margin for a redundancy flag signal and redundancy driving method is improved by sensing generation of an internal address corresponding to an embedded address, and generating a redundancy flag signal, such that the embedded address is an address preceding the address of the memory cell of the normal cell array to be repaired by at least one clock.

摘要翻译： 公开了具有适于修复正常存储器的冗余存储器的突发模式兼容半导体存储器件。 通过感测与嵌入地址相对应的内部地址的生成，并产生冗余标志信号来提高冗余标志信号和冗余驱动方法的响应余量，使得嵌入式地址是地址在存储器单元的地址之前的地址 正常的单元阵列将由至少一个时钟修复。

公开(公告)号：US07313020B2

公开(公告)日：2007-12-25

申请号：US11416064

申请日：2006-05-03

申请人： Dong Hyuk Chae ,  Young Ho Lim

发明人： Dong Hyuk Chae ,  Young Ho Lim

IPC分类号： G11C16/04

CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/5642

摘要： A nonvolatile semiconductor memory device is provided which includes a memory array, a page buffer, and a row decoder. The memory array includes a plurality of nonvolatile memory cells, a bit line, and a word line, and the row decoder driven to control the word line of the memory array. The page buffer is electrically connected to the bit line and includes a main data latch and a sub-data latch. The page buffer, which is configured such that flipping of the main data latch is inhibited according to a logic state of the sub-data latch, further includes a main latch block, a sub-latch block, and a latch control block. The main latch block drives the main data latch and maps a logic state of the main data latch to a threshold voltage of a corresponding memory cell through the bit line. The sub-latch block drives the sub-data latch, where the sub-data latch is flipped depending on the voltage level of the bit line. The latch control block selectively flips the main data latch depending on the voltage level of the bit line, where the latch control block is disabled depending on a logic state of the sub-data latch.

摘要翻译： 提供一种包括存储器阵列，页缓冲器和行解码器的非易失性半导体存储器件。 存储器阵列包括多个非易失性存储器单元，位线和字线，并且行解码器被驱动以控制存储器阵列的字线。 页缓冲器电连接到位线，并包括主数据锁存器和子数据锁存器。 根据子数据锁存器的逻辑状态禁止主数据锁存器翻转的页缓冲器还包括主锁存块，子锁存块和锁存控制块。 主锁存块驱动主数据锁存器，并通过位线将主数据锁存器的逻辑状态映射到相应存储器单元的阈值电压。 子锁存块驱动子数据锁存器，其中子数据锁存器根据位线的电压电平翻转。 锁存控制块根据位线的电压电平有选择地翻转主数据锁存器，根据子数据锁存器的逻辑状态，锁存器控制块被禁用。