公开(公告)号：US12288722B2

公开(公告)日：2025-04-29

申请号：US18149130

申请日：2023-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Jhih-Rong Huang ,  Yen-Tien Tung ,  Tzer-Min Shen ,  Fu-Ting Yen ,  Gary Chan ,  Keng-Chu Lin ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/8234 ,  H01L21/3065 ,  H01L29/66 ,  H01L29/786

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.

公开(公告)号：US12255249B2

公开(公告)日：2025-03-18

申请号：US18446674

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal Abhijith Khaderbad ,  Keng-Chu Lin ,  Yu-Yun Peng

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

Abstract: The present disclosure is directed to method for the fabrication of spacer structures between source/drain epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form spacer cavities, and depositing a spacer layer on the fin structure to fill the spacer cavities. Further, treating the spacer layer with a microwave-generated plasma to form an oxygen concentration gradient within the spacer layer outside the spacer cavities and removing, with an etching process, the treated portion of the spacer layer. During the etching process, a removal rate of the etching process for the treated portion of the spacer layer is based on an oxygen concentration within the oxygen concentration gradient.

公开(公告)号：US20250006687A1

公开(公告)日：2025-01-02

申请号：US18345248

申请日：2023-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zheng-Yong Liang ,  Wei-Ting Yeh ,  Han-De Chen ,  Chen-Fong Tsai ,  Yu-Yun Peng ,  Keng-Chu Lin

IPC: H01L23/00 ,  H01L23/373

Abstract: An integrated circuit die with two material layers having metal nano-particles and the method of forming the same are provided. The integrated circuit die includes a device layer comprising a first transistor, a first interconnect structure on a first side of the device layer, a first material layer on the first interconnect structure, wherein the first material layer comprises first metal nano-particles, and a second material layer bonded to the first material layer, wherein the second material layer comprises second metal nano-particles, and wherein the first material layer and the second material layer share an interface.

公开(公告)号：US12112974B2

公开(公告)日：2024-10-08

申请号：US17860264

申请日：2022-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Tang Peng ,  Shuen-Shin Liang ,  Keng-Chu Lin ,  Teng-Chun Tsai

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/02356 ,  H01L21/76826 ,  H01L21/76837 ,  H01L21/823481

Abstract: Examples of a technique for forming a dielectric material for an integrated circuit are provided herein. In an example, an integrated circuit workpiece is received that includes a recess. A first dielectric precursor is deposited in the recess. The first dielectric precursor includes a non-semiconductor component. A second dielectric precursor is deposited in the recess on the first dielectric precursor, and an annealing process is performed such that a portion of the non-semiconductor component of the first dielectric precursor diffuses into the second dielectric precursor. The non-semiconductor component may include oxygen, and the annealing process may be performed in one of a vacuum or an inert gas environment.

公开(公告)号：US20240258318A1

公开(公告)日：2024-08-01

申请号：US18594073

申请日：2024-03-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal A. Khaderbad ,  Ziwei Fang ,  Keng-Chu Lin ,  Hsueh Wen Tsau

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842

Abstract: An integrated circuit (IC) device includes a semiconductor substrate having a first plurality of stacked semiconductor layers in a p-type transistor region and a second plurality of stacked semiconductor layers in a n-type transistor region. A gate dielectric layer wraps around each of the first and second plurality of stacked semiconductor layers. A first metal gate in the p-type transistor region has a work function metal layer and a first fill metal layer, where the work function metal layer wraps around and is in direct contact with the gate dielectric layer and the first fill metal layer is in direct contact with the work function metal layer. A second metal gate in the n-type transistor region has a second fill metal layer that is in direct contact with the gate dielectric layer, where the second fill metal layer has a work function about equal to or lower than 4.3 eV.

公开(公告)号：US12051592B2

公开(公告)日：2024-07-30

申请号：US17509314

申请日：2021-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Li Wang ,  Hung-Yi Huang ,  Yu-Yun Peng ,  Mrunal A. Khaderbad ,  Chia-Hung Chu ,  Shuen-Shin Liang ,  Keng-Chu Lin

IPC: H01L21/265 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/26586 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76895 ,  H01L23/53209 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/535

Abstract: A method includes receiving a structure having a dielectric layer over a conductive feature, wherein the conductive feature includes a second metal. The method further includes etching a hole through the dielectric layer and exposing the conductive feature and depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature, wherein the first metal entirely fills the hole. The method further includes annealing the structure such that atoms of the second metal are diffused into grain boundaries of the first metal and into interfaces between the first metal and the dielectric layer. After the annealing, the method further includes performing a chemical mechanical planarization (CMP) process to remove at least a portion of the first metal.

公开(公告)号：US20230246082A1

公开(公告)日：2023-08-03

申请号：US18297854

申请日：2023-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hung Chu ,  Tsungyu Hung ,  Hsu-Kai Chang ,  Ding-Kang Shih ,  Keng-Chu Lin ,  Pang-Yen Tsai ,  Sung-Li Wang ,  Shuen-Shin Liang

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285

CPC classification number: H01L29/41733 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66742 ,  H01L29/78696 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28518 ,  H01L29/78618

Abstract: A semiconductor device structure according to the present disclosure includes a source feature and a drain feature, at least one channel structure extending between the source feature and the drain feature, a gate structure wrapped around each of the at least one channel structure, a semiconductor layer over the gate structure, a dielectric layer over the semiconductor layer, a doped semiconductor feature extending through the semiconductor layer and the dielectric layer to be in contact with the source feature, a metal contact plug over the doped semiconductor feature, and a buried power rail disposed over the metal contact plug.

公开(公告)号：US11594609B2

公开(公告)日：2023-02-28

申请号：US16887577

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing, Co., Ltd.

Inventor： Shuen-Shin Liang ,  Chun-I Tsai ,  Chih-Wei Chang ,  Chun-Hsien Huang ,  Hung-Yi Huang ,  Keng-Chu Lin ,  Ken-Yu Chang ,  Sung-Li Wang ,  Chia-Hung Chu ,  Hsu-Kai Chang

IPC: H01L29/45 ,  H01L23/535 ,  H01L21/768

Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes forming a liner-free conductive structure on a cobalt conductive structure disposed on a substrate, depositing a cobalt layer on the liner-free conductive structure and exposing the liner-free conductive structure to a heat treatment. The method further includes removing the cobalt layer from the liner-free conductive structure.

公开(公告)号：US11545397B2

公开(公告)日：2023-01-03

申请号：US17143698

申请日：2021-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu Lin ,  Jhih-Rong Huang ,  Yen-Tien Tung ,  Tzer-Min Shen ,  Fu-Ting Yen ,  Gary Chan ,  Keng-Chu Lin ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/8234 ,  H01L21/3065

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.

公开(公告)号：US11521929B2

公开(公告)日：2022-12-06

申请号：US17141445

申请日：2021-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuen-Shin Liang ,  Chun-I Tsai ,  Chih-Wei Chang ,  Chun-Hsien Huang ,  Hung-Yi Huang ,  Keng-Chu Lin ,  Ken-Yu Chang ,  Sung-Li Wang ,  Chia-Hung Chu ,  Hsu-Kai Chang

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L21/285

Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.