公开(公告)号：US20220367200A1

公开(公告)日：2022-11-17

申请号：US17844563

申请日：2022-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Lun Chang ,  Pin-Chuan Su ,  Hsin-Chieh Huang ,  Ming-Yuan Wu ,  Tzu kai Lin ,  Yu-Wen Wang ,  Che-Yuan Hsu

IPC: H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/02

Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.

公开(公告)号：US20240371649A1

公开(公告)日：2024-11-07

申请号：US18775109

申请日：2024-07-17

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Che-Lun Chang ,  Pin-Chuan Su ,  Hsin-Chieh Huang ,  Ming-Yuan Wu ,  Tzu kai Lin ,  Yu-Wen Wang ,  Che-Yuan Hsu

IPC: H01L21/306 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.

公开(公告)号：US11387109B1

公开(公告)日：2022-07-12

申请号：US17193693

申请日：2021-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Lun Chang ,  Pin-Chuan Su ,  Hsin-Chieh Huang ,  Ming-Yuan Wu ,  Tzu kai Lin ,  Yu-Wen Wang ,  Che-Yuan Hsu, deseased

IPC: H01L21/306 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/308

Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.

公开(公告)号：US09570557B2

公开(公告)日：2017-02-14

申请号：US14700067

申请日：2015-04-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen Cheng Chou ,  Chung-Ren Sun ,  Chii-Ming Wu ,  Cheng-Ta Wu ,  Tzu kai Lin

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L21/225 ,  H01L21/306

CPC classification number: H01L29/1054 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/76237 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: Techniques in fabricating a fin field-effect transistor (FinFET) include providing a substrate having a fin structure and forming an isolation region having a top surface with a first surface profile. A dopant species is implanted using a tilt angle to edge portions of the top surface. The edge portions are then removed using an etch process. In this respect, the isolation region is modified to have a second surface profile based on an etching rate that is greater than an etching rate used at other portions of the top surface. The second surface profile has a step height that is smaller than a step height corresponding to the first surface profile. The tilt implantation and etching process can be performed before a gate structure is formed, after the gate structure is formed but before the fin structure is recessed, or after the fin structure is recessed.

Abstract translation: 制造鳍状场效应晶体管（FinFET）的技术包括提供具有翅片结构的衬底，并形成具有第一表面轮廓的顶表面的隔离区域。 使用与顶表面的边缘部分倾斜的角度注入掺杂剂种类。 然后使用蚀刻工艺除去边缘部分。 在这方面，基于大于在顶表面的其它部分使用的蚀刻速率的蚀刻速率，将隔离区域修改为具有第二表面轮廓。 第二表面轮廓具有小于对应于第一表面轮廓的台阶高度的台阶高度。 倾斜注入和蚀刻处理可以在栅极结构形成之后，在栅极结构形成之后，但在鳍结构凹陷之前，或鳍结构凹陷之后进行。

公开(公告)号：US12131911B2

公开(公告)日：2024-10-29

申请号：US17844563

申请日：2022-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Lun Chang ,  Pin-Chuan Su ,  Hsin-Chieh Huang ,  Ming-Yuan Wu ,  Tzu kai Lin ,  Yu-Wen Wang ,  Che-Yuan Hsu

IPC: H01L21/306 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L21/30625 ,  H01L21/02447 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/66636

Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.