公开(公告)号：US20220367248A1

公开(公告)日：2022-11-17

申请号：US17877824

申请日：2022-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta WU ,  Chii-Ming WU ,  Sen-Hong SYUE ,  Cheng-Po CHAU

IPC: H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78

Abstract: A method includes forming a first trench and a second trench in a semiconductor substrate; forming a first mask over the semiconductor substrate, wherein the first mask is disposed in a first portion of the first trench and exposes the second trench and a second portion of the first trench; after forming the first mask, deepening the second trench and the second portion of the first trench; after deepening the second trench and the second portion of the first trench, removing the first mask; and after removing the first mask, filling a dielectric material in both the first and second trenches.

公开(公告)号：US20190139814A1

公开(公告)日：2019-05-09

申请号：US16222769

申请日：2018-12-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta WU ,  Chii-Ming WU ,  Sen-Hong SYUE ,  Cheng-Po CHAU

IPC: H01L21/762 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06

Abstract: A semiconductor structure includes a semiconductor substrate, a first fin, a second fin, a first isolation structure, and a second isolation structure. The semiconductor substrate has a memory device region and a logic core region. The first fin is in the memory device region of the semiconductor substrate. The second fin is in the logic core region of the semiconductor substrate. The first isolation structure is around the first fin. The second isolation structure is around the second fin, and a thickness of the first isolation structure is different from a thickness of the second isolation structure.

公开(公告)号：US20190131421A1

公开(公告)日：2019-05-02

申请号：US15797973

申请日：2017-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Ku SHEN ,  Jin-Mu YIN ,  Tsung-Chieh HSIAO ,  Chia-Lin CHUANG ,  Li-Zhen YU ,  Dian-Hau CHEN ,  Shih-Wei WANG ,  De-Wei YU ,  Chien-Hao CHEN ,  Bo-Cyuan LU ,  Jr-Hung LI ,  Chi-On CHUI ,  Min-Hsiu HUNG ,  Huang-Yi HUANG ,  Chun-Cheng CHOU ,  Ying-Liang CHUANG ,  Yen-Chun HUANG ,  Chih-Tang PENG ,  Cheng-Po CHAU ,  Yen-Ming CHEN

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/78 ,  H01L21/768 ,  H01L21/3065 ,  H01L21/8234 ,  H01L29/45 ,  H01L27/088 ,  H01L29/08

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.

公开(公告)号：US20210359111A1

公开(公告)日：2021-11-18

申请号：US17109895

申请日：2020-12-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ya-Wen CHIU ,  Yi Che CHAN ,  Lun-Kuang TAN ,  Zheng-Yang PAN ,  Cheng-Po CHAU ,  Pin-Ju LIANG ,  Hung-Yao CHEN ,  De-Wei YU ,  Yi-Cheng LI

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/161 ,  H01L29/10 ,  H01L21/02 ,  H01L21/8238

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.

公开(公告)号：US20190103277A1

公开(公告)日：2019-04-04

申请号：US15952714

申请日：2018-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hongfa LUAN ,  Huicheng CHANG ,  Cheng-Po CHAU ,  Wen-Yu KU ,  Yi-Fan CHEN ,  Chun-Yen PENG

IPC: H01L21/28 ,  H01L21/225 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78

Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.

公开(公告)号：US20210202301A1

公开(公告)日：2021-07-01

申请号：US17200198

申请日：2021-03-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta WU ,  Chii-Ming WU ,  Sen-Hong SYUE ,  Cheng-Po CHAU

IPC: H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78

Abstract: A method includes forming a first trench in a semiconductor substrate. A mask is filled in the first trench and over the semiconductor substrate. After filling the mask in the first trench, the mask is patterned to form an opening in the mask. A second trench is formed in the semiconductor substrate. A depth of the second trench is different from a depth of the first trench. After forming the second trench in the semiconductor substrate, the mask is removed. A dielectric material is filled in both the first and second trenches.

公开(公告)号：US20180151414A1

公开(公告)日：2018-05-31

申请号：US15660107

申请日：2017-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta WU ,  Chii-Ming WU ,  Sen-Hong SYUE ,  Cheng-Po CHAU

IPC: H01L21/762 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/76229 ,  H01L21/76232 ,  H01L21/823412 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/105 ,  H01L27/1463 ,  H01L29/0653 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, a first isolation structure, a second isolation structure STI, and semiconductor fins. The first isolation structure is on the substrate and has a first thickness. The second isolation structure abuts the first isolation structure and has a second thickness. The first thickness is different from the second thickness. The semiconductor fins respectively abut the first isolation structure and the second isolation structure.