公开(公告)号：US20200335388A1

公开(公告)日：2020-10-22

申请号：US16921015

申请日：2020-07-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Teng-Chun TSAI ,  Bing-Hung CHEN ,  Chien-Hsun WANG ,  Cheng-Tung LIN ,  Chih-Tang PENG ,  De-Fang CHEN ,  Huan-Just LIN ,  Li-Ting WANG ,  Yung-Cheng LU

IPC: H01L21/762 ,  H01L21/3105 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  B82Y10/00 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/775 ,  H01L29/06 ,  H01L29/41

Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.

公开(公告)号：US20190164848A1

公开(公告)日：2019-05-30

申请号：US16047115

申请日：2018-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Pin CHUNG ,  Chih-Tang PENG ,  Tien-I BAO

IPC: H01L21/8238 ,  H01L21/762 ,  H01L21/02 ,  H01L27/092

Abstract: A semiconductor structure and a method for forming the same are provided. The method includes forming a first insulation material layer in a portion of a trench between a first protruding structure and a second protruding structure over a substrate and performing a pre-treatment process on the first insulation material layer. The method further includes performing a first insulation material conversion process on the first insulation material layer and forming a second insulation material layer covering the first insulation material layer in the trench. In addition, a first distance between upper portions of the first protruding structure and the second protruding structure before performing the first insulation material conversion process is different from a second distance between the upper portions of the first protruding structure and the second protruding structure after performing the first insulation material conversion process.

公开(公告)号：US20180240882A1

公开(公告)日：2018-08-23

申请号：US15959900

申请日：2018-04-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Tang PENG ,  Tai-Chun HUANG ,  Teng-Chun TSAI ,  Cheng-Tung LIN ,  De-Fang CHEN ,  Li-Ting WANG ,  Chien-Hsun WANG ,  Huan-Just LIN ,  Yung-Cheng LU ,  Tze-Liang LEE

IPC: H01L29/423 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L23/31 ,  H01L23/00 ,  B82Y40/00 ,  B82Y10/00 ,  H01L23/29 ,  H01L29/788 ,  H01L29/775 ,  H01L27/088

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/564 ,  H01L27/088 ,  H01L29/0676 ,  H01L29/42356 ,  H01L29/66272 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/7889 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to an exemplary embodiment, a method of forming a vertical structure with at least two barrier layers is provided. The method includes the following operations: providing a substrate; providing a vertical structure over the substrate; providing a first barrier layer over a source, a channel, and a drain of the vertical structure; and providing a second barrier layer over a gate and the drain of the vertical structure.

公开(公告)号：US20160308027A1

公开(公告)日：2016-10-20

申请号：US14688885

申请日：2015-04-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Wei CHANG ,  An-Shen CHANG ,  Eric Chih-Fang LIU ,  Ryan Chia-Jen CHEN ,  Chia-Tai LIN ,  Chih-Tang PENG

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/3065 ,  H01L21/283 ,  H01L21/306

CPC classification number: H01L29/66795 ,  H01L21/3086

Abstract: A process of manufacturing a Fin-FET device, and the process includes following steps. An active fin structure and a dummy fin structure are formed from a substrate, and an isolation layer is covered over the active fin structure and the dummy fin structure. Then, the isolation layer above the dummy fin structure is removed, and the dummy fin structure is selectively etched, which a selective ratio of the dummy fin structure to the isolation layer is over 8.

Abstract translation: 制造Fin-FET器件的工序，其处理包括以下工序。 由基板形成活动翅片结构和虚拟翅片结构，并且隔离层被覆盖在主动翅片结构和虚拟翅片结构上。 然后，去除虚拟翅片结构上方的隔离层，并且选择性地蚀刻虚拟翅片结构，虚拟鳍结构与隔离层的选择比超过8。

公开(公告)号：US20150318213A1

公开(公告)日：2015-11-05

申请号：US14455598

申请日：2014-08-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Teng-Chun TSAI ,  Li-Ting WANG ,  Cheng-Tung LIN ,  De-Fang CHEN ,  Chih-Tang PENG ,  Chien-Hsun WANG ,  Hung-Ta LIN

IPC: H01L21/8234 ,  H01L29/08 ,  H01L21/265 ,  H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/105 ,  B82Y10/00 ,  H01L21/265 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823487 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/1041 ,  H01L29/1608 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/66356 ,  H01L29/66439 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/7827

Abstract: A tunnel field-effect transistor and method fabricating the same are provided. The tunnel field-effect transistor includes a drain region, a source region with opposite conductive type to the drain region, a channel region disposed between the drain region and the source region, a metal gate layer disposed around the channel region, and a high-k dielectric layer disposed between the metal gate layer and the channel region.

Abstract translation: 提供隧道场效应晶体管及其制造方法。 隧道场效应晶体管包括漏极区域，与漏极区域具有相反导电类型的源极区域，设置在漏极区域和源极区域之间的沟道区域，设置在沟道区域周围的金属栅极层， k电介质层设置在金属栅极层和沟道区之间。

公开(公告)号：US20190287971A1

公开(公告)日：2019-09-19

申请号：US15920967

申请日：2018-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ping LEE ,  Jian-Shiou HUANG ,  Chih-Tang PENG ,  Sung-En LIN

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure protruding from a semiconductor substrate. The fin structure includes a first portion and an overlying second portion. The first portion is formed of a material that is the same as that of the semiconductor substrate and different from that of the second portion. The semiconductor device structure also includes a liner structure and an isolation feature. The liner structure includes a carbon-doped silicon oxide film covering the semiconductor substrate and the first portion of the first fin structure and a nitrogen-containing film over the carbon-doped silicon oxide film. The isolation feature is over the nitrogen-containing film and surrounded by the liner structure.

公开(公告)号：US20190131421A1

公开(公告)日：2019-05-02

申请号：US15797973

申请日：2017-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Ku SHEN ,  Jin-Mu YIN ,  Tsung-Chieh HSIAO ,  Chia-Lin CHUANG ,  Li-Zhen YU ,  Dian-Hau CHEN ,  Shih-Wei WANG ,  De-Wei YU ,  Chien-Hao CHEN ,  Bo-Cyuan LU ,  Jr-Hung LI ,  Chi-On CHUI ,  Min-Hsiu HUNG ,  Huang-Yi HUANG ,  Chun-Cheng CHOU ,  Ying-Liang CHUANG ,  Yen-Chun HUANG ,  Chih-Tang PENG ,  Cheng-Po CHAU ,  Yen-Ming CHEN

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/78 ,  H01L21/768 ,  H01L21/3065 ,  H01L21/8234 ,  H01L29/45 ,  H01L27/088 ,  H01L29/08

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.

公开(公告)号：US20180350655A1

公开(公告)日：2018-12-06

申请号：US16049520

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Teng-Chun TSAI ,  Bing-Hung CHEN ,  Chien-Hsun WANG ,  Cheng-Tung LIN ,  Chih-Tang PENG ,  De-Fang CHEN ,  Huan-Just LIN ,  Li-Ting WANG ,  Yung-Cheng LU

IPC: H01L21/762 ,  H01L21/3105 ,  H01L29/41 ,  H01L29/06 ,  H01L29/775 ,  H01L29/423 ,  H01L21/8238 ,  B82Y10/00 ,  H01L21/311 ,  H01L29/66

Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.

公开(公告)号：US20150318214A1

公开(公告)日：2015-11-05

申请号：US14460214

申请日：2014-08-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Teng-Chun TSAI ,  Cheng-Tung LIN ,  Li-Ting WANG ,  Chih-Tang PENG ,  De-Fang CHEN ,  Hung-Ta LIN ,  Chien-Hsun WANG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/265 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7391 ,  B82Y10/00 ,  H01L21/265 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823487 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/66356 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/66977 ,  H01L29/775 ,  H01L29/7827

Abstract: The tunnel field-effect transistor includes a drain layer, a source layer, a channel layer, a metal gate layer, and a high-k dielectric layer. The drain and source layers are of opposite conductive types. The channel layer is disposed between the drain layer and the source layer. At least one of the drain layer, the channel layer, and the source layer has a substantially constant doping concentration. The metal gate layer is disposed around the channel layer. The high-k dielectric layer is disposed between the metal gate layer and the channel layer.

Abstract translation: 隧道场效应晶体管包括漏极层，源极层，沟道层，金属栅极层和高k电介质层。 漏极和源极层具有相反的导电类型。 沟道层设置在漏极层和源极层之间。 漏极层，沟道层和源极层中的至少一个具有基本恒定的掺杂浓度。 金属栅极层设置在沟道层周围。 高k电介质层设置在金属栅极层和沟道层之间。