公开(公告)号：US20240186275A1

公开(公告)日：2024-06-06

申请号：US18151743

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Wei Chiu ,  Jen-Jui Yu ,  Hsuan-Ting Kuo ,  Cheng-Shiuan Wong ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/13 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/11 ,  H01L25/0652 ,  H01L25/0655 ,  H01L23/3675 ,  H01L23/49833 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13117 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/29193 ,  H01L2224/2929 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/29386 ,  H01L2224/32245 ,  H01L2924/01032 ,  H01L2924/014 ,  H01L2924/0503 ,  H01L2924/05032 ,  H01L2924/0543

Abstract: Semiconductor devices including the use of solder materials and methods of manufacturing are provided. In embodiments the solder materials utilize a first tensile raising material, a second tensile raising material, and a eutectic modifier material. By utilizing the materials a solder material can be formed and used with a reduced presence of needles that may otherwise form during the placement and use of the solder material.

公开(公告)号：US20200152616A1

公开(公告)日：2020-05-14

申请号：US16740463

申请日：2020-01-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsuan-Ting Kuo ,  Ching-Hua Hsieh ,  Cheng-Ting Chen ,  Hsiu-Jen Lin ,  Hao-Jan Pei ,  Yu-Peng Tsai ,  Chia-Lun Chang ,  Chih-Chiang Tsao ,  Philip Yu-Shuan Chung

IPC: H01L25/00 ,  H01L23/522 ,  H01L27/06 ,  H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L21/683 ,  H01L21/56

Abstract: A manufacturing method of a package-on-package structure includes at least the following steps. A plurality of conductive bumps of a first package is attached to a tape carrier. A second package is coupled to the first package opposite to the plurality of conductive bumps. When coupling the second package, the plurality of conductive bumps are deformed to form a plurality of deformed conductive bumps, and a contact area between the tape carrier and the respective deformed conductive bump increases.

公开(公告)号：US20230386862A1

公开(公告)日：2023-11-30

申请号：US18447409

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Hao-Jan Pei ,  Hsuan-Ting Kuo ,  Chih-Chiang Tsao ,  Jen-Jui Yu ,  Philip Yu-Shuan Chung ,  Chia-Lun Chang ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh

IPC: H01L21/50 ,  H01L21/48 ,  H01L23/00 ,  B23K1/00 ,  H01L21/60

CPC classification number: H01L21/50 ,  H01L21/4853 ,  H01L24/10 ,  B23K1/0016 ,  H01L2021/60225 ,  H01L2021/60135

Abstract: A method includes forming regions of solder paste on a redistribution structure, wherein the solder paste has a first melting temperature; forming solder bumps on an interconnect structure, wherein the solder bumps have a second melting temperature that is greater than the first melting temperature; placing the solder bumps on the regions of solder paste; performing a first reflow process at a first reflow temperature for a first duration of time, wherein the first reflow temperature is less than the second melting temperature; and after performing the first reflow process, performing a second reflow process at a second reflow temperature for a second duration of time, wherein the second reflow temperature is greater than the second melting temperature.

公开(公告)号：US11545465B2

公开(公告)日：2023-01-03

申请号：US17113676

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Hui-Min Huang ,  Hsuan-Ting Kuo ,  Ming-Da Cheng

IPC: H01L23/02 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.

公开(公告)号：US20220359356A1

公开(公告)日：2022-11-10

申请号：US17870423

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chiang Tsao ,  Chao-Wei Chiu ,  Hsuan-Ting Kuo ,  Chia-Lun Chang ,  Cheng-Shiuan Wong ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A device may include a first package and a second package where the first package has a warped shape. First connectors attached to a redistribution structure of the first package include a spacer embedded therein. Second connectors attached to the redistribution structure are fee from the spacer, the spacer of the first connectors keeping a minimum distance between the first package and the second package during attaching the first package to the second package.

公开(公告)号：US20220216071A1

公开(公告)日：2022-07-07

申请号：US17141835

申请日：2021-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Hao-Jan Pei ,  Hsuan-Ting Kuo ,  Chih-Chiang Tsao ,  Jen-Jui Yu ,  Philip Yu-Shuan Chung ,  Chia-Lun Chang ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh

IPC: H01L21/50 ,  H01L23/00 ,  H01L21/48

Abstract: A method includes forming regions of solder paste on a redistribution structure, wherein the solder paste has a first melting temperature; forming solder bumps on an interconnect structure, wherein the solder bumps have a second melting temperature that is greater than the first melting temperature; placing the solder bumps on the regions of solder paste; performing a first reflow process at a first reflow temperature for a first duration of time, wherein the first reflow temperature is less than the second melting temperature; and after performing the first reflow process, performing a second reflow process at a second reflow temperature for a second duration of time, wherein the second reflow temperature is greater than the second melting temperature.

公开(公告)号：US20250093593A1

公开(公告)日：2025-03-20

申请号：US18403531

申请日：2024-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chih Lin ,  Cheng-Yu Kuo ,  Yen-Hung Chen ,  Hsuan-Ting Kuo ,  Chia-Shen Cheng ,  Chao-Wei Li ,  Ching-Hua Hsieh ,  Wen-Chih Chiou ,  Ming-Fa Chen ,  Shang-Yun Hou

IPC: G02B6/42

Abstract: Optical devices and methods of manufacture are presented in which a mirror structure is utilized to transmit and receive optical signals to and from an optical device. In embodiments the mirror structure receives optical signals from outside of an optical device and directs the optical signals through at least one mirror to an optical component of the optical device.

公开(公告)号：US20250087652A1

公开(公告)日：2025-03-13

申请号：US18405844

申请日：2024-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Cheng-Shiuan Wong ,  Chia-Shen Cheng ,  Hsuan-Ting Kuo ,  Hao-Jan Pei ,  Hsiu-Jen Lin ,  Mao-Yen Chang

IPC: H01L25/18 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00

Abstract: A semiconductor package includes an interposer that has a first side and a second side opposing the first side. A semiconductor device that is on the first side of the interposer and an optical device that is on the first side of the interposer and next to the semiconductor device. A first encapsulant layer includes a first portion and a second portion. The first portion of the first encapsulant layer is on the first side of the interposer and along sidewalls of the semiconductor device. A gap is between a first sidewall of the optical device and a second sidewall of the first portion of the first encapsulant layer. A substrate is over the second side of the interposer. The semiconductor device and the optical device are electrically coupled to the substrate through the interposer.

公开(公告)号：US20250062181A1

公开(公告)日：2025-02-20

申请号：US18507726

申请日：2023-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Wei Chiu ,  Hsuan-Ting Kuo ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: A method includes depositing a first metal layer on a package component, wherein the package component comprises a first device die, forming a dielectric layer on the package component, and plating a metal thermal interface material on the first metal layer. The dielectric layer includes portions on opposing sides of the metal thermal interface material. A heat sink is bonded on the metal thermal interface material. The heat sink includes a second metal layer physically joined to the metal thermal interface material.

公开(公告)号：US12009345B2

公开(公告)日：2024-06-11

申请号：US18149509

申请日：2023-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Hui-Min Huang ,  Hsuan-Ting Kuo ,  Ming-Da Cheng

IPC: H01L23/02 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76804 ,  H01L21/7684 ,  H01L21/76883 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06586

Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.