公开(公告)号：US20160225906A1

公开(公告)日：2016-08-04

申请号：US14613663

申请日：2015-02-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Tsan-Chun WANG ,  Ziwei FANG ,  Chien-Tai CHAN ,  Da-Wen LIN ,  Huicheng CHANG

IPC: H01L29/78 ,  H01L21/266 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L29/7856 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L29/66795

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a doped region in an upper portion of the substrate. The doped region is doped with first dopants of a first conduction type. The semiconductor device structure includes one fin structure over the substrate. A first dopant concentration of the doped region exposed by the fin structure is greater than a second dopant concentration of the doped region covered by the fin structure. The semiconductor device structure includes an isolation layer over the substrate and at two opposite sides of the fin structure. The semiconductor device structure includes a gate over the isolation layer and the fin structure.

Abstract translation: 提供半导体器件结构。 半导体器件结构包括在衬底的上部具有掺杂区的衬底。 掺杂区域掺杂有第一导电类型的第一掺杂剂。 半导体器件结构包括在衬底上的一个鳍结构。 通过鳍结构暴露的掺杂区域的第一掺杂剂浓度大于由鳍结构覆盖的掺杂区域的第二掺杂剂浓度。 半导体器件结构包括在衬底上并在鳍结构的两个相对侧的隔离层。 半导体器件结构包括隔离层上的栅极和鳍结构。

公开(公告)号：US20190067283A1

公开(公告)日：2019-02-28

申请号：US15688478

申请日：2017-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yin WANG ,  Chien-Chih LIN ,  Chien-Tai CHAN ,  Wei-Ken LIN ,  Chun-Te LI

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/417 ,  H01L21/324

Abstract: A fin field-effect transistor (FinFET) structure and a method for forming the same are provided. The FinFET structure includes a first fin structure that protrudes from a first region of a substrate. A second fin structure protrudes from a second region of the substrate. Isolation regions cover lower portions of the first fin structure and the second fin structure and leave upper portions of the first fin structure and the second fin structure above the isolation regions. A first liner layer is positioned between the lower portion of the first fin structure and the isolation regions in the first region. A second liner layer covers the lower portion of the second fin structure and is positioned between the second fin structure and the isolation regions in the second region. The first liner layer and the second liner layer are formed of different materials.

公开(公告)号：US20160204255A1

公开(公告)日：2016-07-14

申请号：US15076762

申请日：2016-03-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Pin LIN ,  Chien-Tai CHAN ,  Hsien-Chin LIN ,  Shyue-Shyh LIN

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/161 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L21/823431 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.

Abstract translation: 一种方法包括形成在半导体衬底之上延伸的finFET的第一和第二鳍片，其间具有浅沟槽隔离（STI）区域，以及STI区域的顶表面与第一鳍片和第二鳍片的顶表面之间的距离。 第一和第二鳍片延伸部分设置在STI区域顶表面上方的第一和第二鳍片的顶表面和侧表面上。 从STI区域去除材料，以增加STI区域的顶表面与第一和第二鳍片的顶表面之间的距离。 保形应力源电介质材料沉积在鳍片和STI区域上。 共形介电应力材料被回流，以流入STI区域的顶表面之上的第一和第二鳍片之间的空间，以向finFET的沟道施加应力。

公开(公告)号：US20160149040A1

公开(公告)日：2016-05-26

申请号：US14819602

申请日：2015-08-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang LEE ,  Ting-Yeh CHEN ,  Chia-Ling CHAN ,  Chien-Tai CHAN

IPC: H01L29/78

CPC classification number: H01L29/7851 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/785

Abstract: A FinFET includes a fin structure, a gate and a source-drain region. The fin structure is over a substrate and has a recess of an upper surface of the fin structure and a doped region in the fin structure and adjacent to the recess. The gate protrudes from the recess and across over the fin structure. The source-drain region is in the fin structure and adjacent to the doped region. Methods for forming the FinFET are also provided.

Abstract translation: FinFET包括鳍结构，栅极和源极 - 漏极区域。 翅片结构在衬底之上，并且具有翅片结构的上表面的凹部和鳍结构中的与凹部相邻的掺杂区域。 门从凹槽突出并跨过翅片结构。 源极 - 漏极区域处于鳍状结构并且与掺杂区域相邻。 还提供了形成FinFET的方法。

公开(公告)号：US20150115322A1

公开(公告)日：2015-04-30

申请号：US14554179

申请日：2014-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Kai CHEN ,  Hsien-Hsin LIN ,  Chia-Pin LIN ,  Chien-Tai CHAN ,  Yuan-Ching PENG

IPC: H01L27/092 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

Abstract: A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the top surface of the STI region and top surfaces of the first and second fins. A flowable dielectric material is deposited into the space. The dielectric material has a top surface above the top surface of the STI region, so as to define a second height between the top surface of the dielectric material and the top surfaces of the first and second fins. The second height is less than the first height. First and second fin extensions are epitaxially formed above the dielectric, on the first and second fins, respectively, after the depositing step.

Abstract translation: 一种方法包括形成在半导体衬底之上延伸的第一鳍片和第二鳍片，在它们之间具有浅沟槽隔离（STI）区域。 在STI区域的顶表面之上的第一和第二鳍之间限定空间。 第一高度限定在STI区域的顶表面和第一鳍片和第二鳍片的顶表面之间。 可流动的电介质材料沉积到该空间中。 电介质材料具有在STI区域的顶表面上方的顶表面，以便在介电材料的顶表面和第一和第二鳍片的顶表面之间限定第二高度。 第二个高度小于第一个高度。 在沉积步骤之后，第一和第二鳍片延伸部分别外延形成在电介质上方，分别在第一和第二鳍片上。

公开(公告)号：US20220059679A1

公开(公告)日：2022-02-24

申请号：US16996665

申请日：2020-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao LIU ,  Huicheng CHANG ,  Chien-Tai CHAN ,  Liang-Yin CHEN ,  Yee-Chia YEO ,  Szu-Ying CHEN

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first fin structure with a first height and a first width formed over the substrate, a second fin structure with a second height and a second width formed over the substrate, and an insulating stack formed over lower portions of the first and second fin structures. The second height can be substantially equal to the first height and the second width can be greater than the first width. A top surface of the insulating stack can be below top surfaces of the first and second fin structures.

公开(公告)号：US20190181048A1

公开(公告)日：2019-06-13

申请号：US16271522

申请日：2019-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Pin LIN ,  Chien-Tai CHAN ,  Hsien-Chin LIN ,  Shyue-Shyh LIN

IPC: H01L21/8234 ,  H01L29/161 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L21/8238

CPC classification number: H01L21/823431 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.

公开(公告)号：US20170110550A1

公开(公告)日：2017-04-20

申请号：US15062062

申请日：2016-03-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung TSAI ,  Kuo-Feng YU ,  Chien-Tai CHAN ,  Ziwei FANG ,  Kei-Wei CHEN ,  Huai-Tei YANG

IPC: H01L29/49 ,  H01L29/40 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L21/2254 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/785

Abstract: A gate structure, a semiconductor device, and the method of forming a semiconductor device are provided. In various embodiments, the gate structure includes a gate stack and a doped spacer overlying a sidewall of the gate stack. The gate stack contains a doped work function metal (WFM) stack and a metal gate electrode overlying the doped WFM stack.