公开(公告)号：US20240258263A1

公开(公告)日：2024-08-01

申请号：US18631900

申请日：2024-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hsien Huang ,  Yao-Chun Chuang ,  SyuFong Li ,  Ching-Pin Lin ,  Jun He

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/683 ,  H01L23/48

CPC classification number: H01L24/27 ,  H01L21/6835 ,  H01L22/14 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/30 ,  H01L2224/0384 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/06515 ,  H01L2224/275 ,  H01L2224/30181 ,  H01L2924/30105 ,  H01L2924/35121 ,  H01L2924/37001

Abstract: In an embodiment, a method includes attaching a first package component to a first carrier, the first package component comprising: an aluminum pad disposed adjacent to a substrate; a sacrificial pad disposed adjacent to the substrate, the sacrificial pad comprising a major surface opposite the substrate, a protrusion of the sacrificial pad extending from the major surface; and a dielectric bond layer disposed around the aluminum pad and the sacrificial pad; attaching a second carrier to the first package component and the first carrier, the first package component being interposed between the first carrier and the second carrier; removing the first carrier; planarizing the dielectric bond layer to comprise a top surface being coplanar with the protrusion; and etching a portion of the protrusion.

公开(公告)号：US12159921B2

公开(公告)日：2024-12-03

申请号：US17881317

申请日：2022-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Chih Chen ,  Ru-Shang Hsiao ,  Ching-Pin Lin ,  Chih-Mu Huang ,  Fu-Tsun Tsai

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423

Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.

公开(公告)号：US20230045422A1

公开(公告)日：2023-02-09

申请号：US17678774

申请日：2022-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hsien Huang ,  Yao-Chun Chuang ,  SyuFong Li ,  Ching-Pin Lin ,  Jun He

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/683 ,  H01L23/48

Abstract: In an embodiment, a method includes attaching a first package component to a first carrier, the first package component comprising: an aluminum pad disposed adjacent to a substrate; a sacrificial pad disposed adjacent to the substrate, the sacrificial pad comprising a major surface opposite the substrate, a protrusion of the sacrificial pad extending from the major surface; and a dielectric bond layer disposed around the aluminum pad and the sacrificial pad; attaching a second carrier to the first package component and the first carrier, the first package component being interposed between the first carrier and the second carrier; removing the first carrier; planarizing the dielectric bond layer to comprise a top surface being coplanar with the protrusion; and etching a portion of the protrusion.

公开(公告)号：US12046566B2

公开(公告)日：2024-07-23

申请号：US17481003

申请日：2021-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Ku ,  Yao-Chun Chuang ,  Ching-Pin Lin ,  Cheng-Chien Li

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/58

CPC classification number: H01L23/585 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/564

Abstract: A semiconductor article which includes a semiconductor substrate, a back end of the line (BEOL) wiring portion on the semiconductor substrate, a through silicon via and a guard ring. The semiconductor substrate is made of a semiconductor material. The BEOL wiring portion includes a plurality of wiring layers having electrically conductive wiring and electrical insulating material. The through silicon via provides a conductive path through the BEOL wiring portion and the semiconductor substrate. The guard ring surrounds the through silicon via in the BEOL wiring portion and in some embodiments in the semiconductor substrate.

公开(公告)号：US11437495B2

公开(公告)日：2022-09-06

申请号：US17157180

申请日：2021-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Chih Chen ,  Ru-Shang Hsiao ,  Ching-Pin Lin ,  Chih-Mu Huang ,  Fu-Tsun Tsai

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423

Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.

公开(公告)号：US10056455B1

公开(公告)日：2018-08-21

申请号：US15800097

申请日：2017-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Chun Kuan ,  I-Chih Chen ,  Chih-Mu Huang ,  Ching-Pin Lin ,  Fu-Tsun Tsai ,  Ru-Shang Hsiao

IPC: H01L29/06 ,  H01L29/08 ,  H01L27/088 ,  H01L21/02 ,  H01L23/532 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/0843 ,  H01L21/02107 ,  H01L21/0243 ,  H01L21/02639 ,  H01L23/53295 ,  H01L27/088 ,  H01L27/0883 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/1083 ,  H01L29/42312 ,  H01L29/42316 ,  H01L29/4232

Abstract: A semiconductor device including a substrate, a gate stack, a pair of insulator structures, and source/drain materials is provided. The substrate has a plurality of recesses, wherein the plurality of recesses defines a protruded portion of the substrate having a channel region, and the protruded portion has a first side surface and a second side surface opposite to the first side surface. The gate stack is disposed on the protruded portion of the substrate. The pair of insulator structures are disposed within the plurality of recesses and respectively covering parts of the first side surface and the second side surface of the protruded portion, wherein the channel region is uncovered by the pair of insulator structures. The source/drain materials are disposed on the substrate in the plurality of recesses and on two opposing sides of the channel region, wherein the source/drain materials cover the pair of insulator structures.

公开(公告)号：US11984422B2

公开(公告)日：2024-05-14

申请号：US17678774

申请日：2022-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hsien Huang ,  Yao-Chun Chuang ,  SyuFong Li ,  Ching-Pin Lin ,  Jun He

IPC: H01L21/683 ,  H01L21/66 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L24/27 ,  H01L21/6835 ,  H01L22/14 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/30 ,  H01L2224/0384 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/06515 ,  H01L2224/275 ,  H01L2224/30181 ,  H01L2924/30105 ,  H01L2924/35121 ,  H01L2924/37001

Abstract: In an embodiment, a method includes attaching a first package component to a first carrier, the first package component comprising: an aluminum pad disposed adjacent to a substrate; a sacrificial pad disposed adjacent to the substrate, the sacrificial pad comprising a major surface opposite the substrate, a protrusion of the sacrificial pad extending from the major surface; and a dielectric bond layer disposed around the aluminum pad and the sacrificial pad; attaching a second carrier to the first package component and the first carrier, the first package component being interposed between the first carrier and the second carrier; removing the first carrier; planarizing the dielectric bond layer to comprise a top surface being coplanar with the protrusion; and etching a portion of the protrusion.

公开(公告)号：US10903336B2

公开(公告)日：2021-01-26

申请号：US16180623

申请日：2018-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Chih Chen ,  Ru-Shang Hsiao ,  Ching-Pin Lin ,  Chih-Mu Huang ,  Fu-Tsun Tsai

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423

Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.

公开(公告)号：US20190165126A1

公开(公告)日：2019-05-30

申请号：US16180623

申请日：2018-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Chih CHEN ,  Ru-Shang Hsiao ,  Ching-Pin Lin ,  Chih-Mu Huang ,  Fu-Tsun Tsai

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234

Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.

公开(公告)号：US10153278B1

公开(公告)日：2018-12-11

申请号：US15717972

申请日：2017-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Lin Hsieh ,  I-Chih Chen ,  Chih-Mu Huang ,  Ching-Pin Lin ,  Ru-Shang Hsiao ,  Ting-Chun Kuan

IPC: H01L27/08 ,  H01L27/088 ,  H01L29/10 ,  H01L29/08 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/06 ,  H01L29/167 ,  H01L21/308 ,  H01L29/78 ,  H01L29/165

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate stack, spacers and epitaxy material portions is described. The substrate has fins and insulators located between the fins, and the fins comprise channel portions and flank portions beside the channel portions, the flank portions and the channel portions of the fins are protruded from the insulators, the flank portions of the fins and the channel portions of the fins have substantially a same height from top surfaces of the insulators, and each of the flank portions of the fins has a top surface and side surfaces adjoining the top surface. The at least one gate stack is disposed over the substrate, disposed on the insulators and over the channel portions of the fins. The spacers are disposed on the side surfaces of the flank portions of the fins. The epitaxy material portions are located above the top surfaces of the flank portions of the fins.