公开(公告)号：US11276699B2

公开(公告)日：2022-03-15

申请号：US16721565

申请日：2019-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chang Wu ,  Chihy-Yuan Cheng ,  Sz-Fan Chen ,  Shun-Shing Yang ,  Wei-Lin Chang ,  Ching-Sen Kuo ,  Feng-Jia Shiu ,  Chun-Chang Chen

IPC: H01L27/11529 ,  H01L27/11546 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/027 ,  H01L27/11521 ,  H01L29/66 ,  H01L29/423 ,  H01L23/544 ,  H01L27/11524 ,  H01L29/49 ,  H01L29/51

Abstract: A wafer having a first region and a second region is provided. A first topography variation exists between the first region and the second region. A first layer is formed over the first region and over the second region of the wafer. The first layer is patterned. A patterned first layer causes a second topography variation to exist between the first region and the second region. The second topography variation is smoother than the first topography variation. A second layer is formed over the first region and the second region. At least a portion of the second layer is formed over the patterned first layer.

公开(公告)号：US20180076081A1

公开(公告)日：2018-03-15

申请号：US15260555

申请日：2016-09-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chihy-Yuan Cheng ,  Chun-Chang Wu ,  Shun-Shing Yang ,  Ching-Sen Kuo ,  Feng-Jia Shiu ,  Chun-Chang Chen

IPC: H01L21/765 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L21/765 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0619

Abstract: A method includes forming a patterned layer on a substrate having a first region and a second region being adjacent each other. The patterned layer includes first features in the first region. The second region is free of the patterned layer. The method further includes forming a material layer on the patterned layer and the substrate; forming a first guard ring disposed in the second region and surrounding the first features; forming a flowable-material (FM) layer over the material layer; forming a patterned resist layer over the FM layer, wherein the patterned resist layer includes a plurality of openings; and transferring the plurality of openings to the material layer.

公开(公告)号：US20220199636A1

公开(公告)日：2022-06-23

申请号：US17694320

申请日：2022-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chang Wu ,  Chihy-Yuan Cheng ,  Sz-Fan Chen ,  Shun-Shing Yang ,  Wei-Lin Chang ,  Ching-Sen Kuo ,  Feng-Jia Shiu ,  Chun-Chang Chen

IPC: H01L27/11546 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/027 ,  H01L27/11521 ,  H01L29/66 ,  H01L29/423 ,  H01L23/544 ,  H01L27/11524

Abstract: A wafer having a first region and a second region is provided. A first topography variation exists between the first region and the second region. A first layer is formed over the first region and over the second region of the wafer. The first layer is patterned. A patterned first layer causes a second topography variation to exist between the first region and the second region. The second topography variation is smoother than the first topography variation. A second layer is formed over the first region and the second region. At least a portion of the second layer is formed over the patterned first layer.

公开(公告)号：US10366916B2

公开(公告)日：2019-07-30

申请号：US15918623

申请日：2018-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chihy-Yuan Cheng ,  Chun-Chang Wu ,  Shun-Shing Yang ,  Ching-Sen Kuo ,  Feng-Jia Shiu ,  Chun-Chang Chen

IPC: H01L21/84 ,  H01L29/06 ,  H01L21/765 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor structure includes a substrate having a first region and a second region being adjacent each other; a first patterned layer formed on the substrate, wherein the first patterned layer includes first features in the first region, wherein the second region is free of the patterned layer; and a first guard ring disposed in the second region and surrounding the first features, wherein the first guard ring includes a first width W1 and is spaced a first distance D1 from the first features, W1 being greater than D1.

公开(公告)号：US11665897B2

公开(公告)日：2023-05-30

申请号：US17694320

申请日：2022-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chang Wu ,  Chihy-Yuan Cheng ,  Sz-Fan Chen ,  Shun-Shing Yang ,  Wei-Lin Chang ,  Ching-Sen Kuo ,  Feng-Jia Shiu ,  Chun-Chang Chen

IPC: H01L27/11546 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/027 ,  H01L27/11521 ,  H01L29/66 ,  H01L29/423 ,  H01L23/544 ,  H01L27/11524 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L27/11546 ,  H01L21/0276 ,  H01L21/31058 ,  H01L21/31111 ,  H01L21/31144 ,  H01L23/544 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L2223/5442 ,  H01L2223/54426

Abstract: A wafer having a first region and a second region is provided. A first topography variation exists between the first region and the second region. A first layer is formed over the first region and over the second region of the wafer. The first layer is patterned. A patterned first layer causes a second topography variation to exist between the first region and the second region. The second topography variation is smoother than the first topography variation. A second layer is formed over the first region and the second region. At least a portion of the second layer is formed over the patterned first layer.

公开(公告)号：US10522557B2

公开(公告)日：2019-12-31

申请号：US15796992

申请日：2017-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chang Wu ,  Chihy-Yuan Cheng ,  Sz-Fan Chen ,  Shun-Shing Yang ,  Wei-Lin Chang ,  Ching-Sen Kuo ,  Feng-Jia Shiu ,  Chun-Chang Chen

IPC: H01L27/11546 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/027 ,  H01L27/11521 ,  H01L29/66 ,  H01L29/423 ,  H01L23/544 ,  H01L27/11524 ,  H01L29/49 ,  H01L29/51

Abstract: A wafer having a first region and a second region is provided. A first topography variation exists between the first region and the second region. A first layer is formed over the first region and over the second region of the wafer. The first layer is patterned. A patterned first layer causes a second topography variation to exist between the first region and the second region. The second topography variation is smoother than the first topography variation. A second layer is formed over the first region and the second region. At least a portion of the second layer is formed over the patterned first layer.

公开(公告)号：US20190131313A1

公开(公告)日：2019-05-02

申请号：US15796992

申请日：2017-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chang Wu ,  Chihy-Yuan Cheng ,  Sz-Fan Chen ,  Shun-Shing Yang ,  Wei-Lin Chang ,  Ching-Sen Kuo ,  Feng-Jia Shiu ,  Chun-Chang Chen

IPC: H01L27/11546 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/027 ,  H01L27/11521 ,  H01L29/423 ,  H01L23/544

Abstract: A wafer having a first region and a second region is provided. A first topography variation exists between the first region and the second region. A first layer is formed over the first region and over the second region of the wafer. The first layer is patterned. A patterned first layer causes a second topography variation to exist between the first region and the second region. The second topography variation is smoother than the first topography variation. A second layer is formed over the first region and the second region. At least a portion of the second layer is formed over the patterned first layer.

公开(公告)号：US20180204758A1

公开(公告)日：2018-07-19

申请号：US15918623

申请日：2018-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chihy-Yuan Cheng ,  Chun-Chang Wu ,  Shun-Shing Yang ,  Ching-Sen Kuo ,  Feng-Jia Shiu ,  Chun-Chang Chen

IPC: H01L21/765 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L21/765 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0619

Abstract: A semiconductor structure includes a substrate having a first region and a second region being adjacent each other; a first patterned layer formed on the substrate, wherein the first patterned layer includes first features in the first region, wherein the second region is free of the patterned layer; and a first guard ring disposed in the second region and surrounding the first features, wherein the first guard ring includes a first width W1 and is spaced a first distance D1 from the first features, W1 being greater than D1.

公开(公告)号：US09917006B1

公开(公告)日：2018-03-13

申请号：US15260555

申请日：2016-09-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chihy-Yuan Cheng ,  Chun-Chang Wu ,  Shun-Shing Yang ,  Ching-Sen Kuo ,  Feng-Jia Shiu ,  Chun-Chang Chen

IPC: H01L27/00 ,  H01L21/765 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L21/765 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0619

Abstract: A method includes forming a patterned layer on a substrate having a first region and a second region being adjacent each other. The patterned layer includes first features in the first region. The second region is free of the patterned layer. The method further includes forming a material layer on the patterned layer and the substrate; forming a first guard ring disposed in the second region and surrounding the first features; forming a flowable-material (FM) layer over the material layer; forming a patterned resist layer over the FM layer, wherein the patterned resist layer includes a plurality of openings; and transferring the plurality of openings to the material layer.