公开(公告)号：US10515807B1

公开(公告)日：2019-12-24

申请号：US16008321

申请日：2018-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Fen Chien ,  Chih-Hsiang Fan ,  Hsiao-Kuan Wei ,  Pohan Kung ,  Hsien-Ming Lee

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L21/321 ,  H01L29/06

Abstract: Methods of fabricating semiconductor devices are provided. The method includes forming a gate dielectric layer over a substrate. The method also includes depositing a first p-type work function tuning layer over the gate dielectric layer using a first atomic layer deposition (ALD) process with an inorganic precursor. The method further includes forming a second p-type work function tuning layer on the first p-type work function tuning layer using a second atomic layer deposition (ALD) process with an organic precursor. In addition, the method includes forming an n-type work function metal layer over the second p-type work function tuning layer.

公开(公告)号：US11380542B2

公开(公告)日：2022-07-05

申请号：US17013316

申请日：2020-09-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chien Chi ,  Pei-Hsuan Lee ,  Hung-Wen Su ,  Hsiao-Kuan Wei ,  Jui-Fen Chien ,  Hsin-Yun Hsu

IPC: H01L21/02 ,  H01L21/20 ,  H01L29/66 ,  H01L21/762 ,  H01L29/49 ,  H01L21/324 ,  H01L21/28 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/3205 ,  H01L29/417 ,  H01L21/3105 ,  H01L21/768

Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

公开(公告)号：US20200287014A1

公开(公告)日：2020-09-10

申请号：US16884053

申请日：2020-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Fen Chien ,  Hsiao-Kuan Wei ,  Hsien-Ming Lee ,  Chin-You Hsu

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L21/28

Abstract: Provided is a semiconductor device including a first n-type fin field effect transistor (FinFET) and a second n-type FinFET. The first FinFET includes a first work function layer. The first work function layer includes a first portion of a first layer. The second n-type FinFET includes a second work function layer. The second work function layer includes a second portion of the first layer and a first portion of a second layer underlying the second portion of the first layer. A thickness of the first work function layer is less than a thickness of the second work function layer. A method of manufacturing the semiconductor device is also provided.

公开(公告)号：US20190148510A1

公开(公告)日：2019-05-16

申请号：US15877391

申请日：2018-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Fen Chien ,  Hsiao-Kuan Wei ,  Hsien-Ming Lee ,  Chin-You Hsu

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L27/092

Abstract: Provided is a semiconductor device including a fin-type field effect transistor (FinFET). The first FinFET includes a first gate structure and the first gate structure includes a first work function layer. The first work function layer includes a first layer and a second layer. The first layer is disposed over the second layer. The second layer includes a base material and a dopant doped in the base material. The dopant comprises Al, Ta, W, or a combination thereof. The first layer and the second layer comprise different materials. A method of manufacturing the semiconductor device is also provided.

公开(公告)号：US11830742B2

公开(公告)日：2023-11-28

申请号：US17853600

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chien Chi ,  Pei-Hsuan Lee ,  Hung-Wen Su ,  Hsiao-Kuan Wei ,  Jui-Fen Chien ,  Hsin-Yun Hsu

IPC: H01L21/02 ,  H01L21/20 ,  H01L29/66 ,  H01L21/762 ,  H01L29/49 ,  H01L21/324 ,  H01L21/28 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/3205 ,  H01L29/417 ,  H01L21/3105 ,  H01L21/768

CPC classification number: H01L21/3105 ,  H01L21/02362 ,  H01L21/02639 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/3245 ,  H01L21/32051 ,  H01L21/768 ,  H01L21/76262 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/4238 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/76224

Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

公开(公告)号：US11698423B2

公开(公告)日：2023-07-11

申请号：US16991424

申请日：2020-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Fen Chien ,  Wei-Gang Chiu ,  Tsann Lin

IPC: G11C11/16 ,  G01R33/09 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: G01R33/093 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  H10B61/22 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: In an embodiment, a device includes: a magnetoresistive random access memory cell including: a bottom electrode; a reference layer over the bottom electrode; a tunnel barrier layer over the reference layer, the tunnel barrier layer including a first composition of magnesium and oxygen; a free layer over the tunnel barrier layer, the free layer having a lesser coercivity than the reference layer; a cap layer over the free layer, the cap layer including a second composition of magnesium and oxygen, the second composition of magnesium and oxygen having a greater atomic concentration of oxygen and a lesser atomic concentration of magnesium than the first composition of magnesium and oxygen; and a top electrode over the cap layer.

公开(公告)号：US20220328309A1

公开(公告)日：2022-10-13

申请号：US17853600

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chien Chi ,  Pei-Hsuan Lee ,  Hung-Wen Su ,  Hsiao-Kuan Wei ,  Jui-Fen Chien ,  Hsin-Yun Hsu

IPC: H01L21/02 ,  H01L21/20 ,  H01L29/66 ,  H01L21/762 ,  H01L29/49 ,  H01L21/324 ,  H01L21/28 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/3205 ,  H01L29/417 ,  H01L21/3105 ,  H01L21/768

Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

公开(公告)号：US10790142B2

公开(公告)日：2020-09-29

申请号：US15880389

申请日：2018-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chien Chi ,  Hsiao-Kuan Wei ,  Hung-Wen Su ,  Pei-Hsuan Lee ,  Hsin-Yun Hsu ,  Jui-Fen Chien

IPC: H01L21/02 ,  H01L21/20 ,  H01L29/66 ,  H01L21/762 ,  H01L29/49 ,  H01L29/423 ,  H01L21/28 ,  H01L27/092 ,  H01L21/324 ,  H01L29/78 ,  H01L21/3205 ,  H01L29/417 ,  H01L21/3105 ,  H01L21/768

Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

公开(公告)号：US10707318B2

公开(公告)日：2020-07-07

申请号：US15877391

申请日：2018-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Fen Chien ,  Hsiao-Kuan Wei ,  Hsien-Ming Lee ,  Chin-You Hsu

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L21/28 ,  H01L29/165

Abstract: Provided is a semiconductor device including a fin-type field effect transistor (FinFET). The first FinFET includes a first gate structure and the first gate structure includes a first work function layer. The first work function layer includes a first layer and a second layer. The first layer is disposed over the second layer. The second layer includes a base material and a dopant doped in the base material. The dopant comprises Al, Ta, W, or a combination thereof. The first layer and the second layer comprise different materials. A method of manufacturing the semiconductor device is also provided.

公开(公告)号：US12298362B2

公开(公告)日：2025-05-13

申请号：US18324368

申请日：2023-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Fen Chien ,  Wei-Gang Chiu ,  Tsann Lin

IPC: G01R33/09 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: In an embodiment, a device includes: a magnetoresistive random access memory cell including: a bottom electrode; a reference layer over the bottom electrode; a tunnel barrier layer over the reference layer, the tunnel barrier layer including a first composition of magnesium and oxygen; a free layer over the tunnel barrier layer, the free layer having a lesser coercivity than the reference layer; a cap layer over the free layer, the cap layer including a second composition of magnesium and oxygen, the second composition of magnesium and oxygen having a greater atomic concentration of oxygen and a lesser atomic concentration of magnesium than the first composition of magnesium and oxygen; and a top electrode over the cap layer.