Planarization control in semiconductor manufacturing process

    公开(公告)号:US10541139B2

    公开(公告)日:2020-01-21

    申请号:US15079243

    申请日:2016-03-24

    Abstract: A method of forming a semiconductor device includes forming fins on a substrate, depositing a gate layer having a first material on the fins, and depositing a sacrificial layer having a second material on the gate layer. The method further includes removing a first portion of the sacrificial layer using a first slurry or etchant having a first selectivity of second material to first material. The method further includes removing a first portion of the gate layer and a second portion of the sacrificial layer using a second slurry or etchant having a second selectivity of second material to first material to form a planarized gate layer. The first selectivity is greater than the second selectivity. An example benefit includes reduced dependency of the gate layer planarization process on underlying structure density and reduced variation in thickness of the gate layer on device structures across a wafer.

    Planarization Control in Semiconductor Manufacturing Process

    公开(公告)号:US20170278712A1

    公开(公告)日:2017-09-28

    申请号:US15079243

    申请日:2016-03-24

    Abstract: A method of forming a semiconductor device includes forming fins on a substrate, depositing a gate layer having a first material on the fins, and depositing a sacrificial layer having a second material on the gate layer. The method further includes removing a first portion of the sacrificial layer using a first slurry or etchant having a first selectivity of second material to first material. The method further includes removing a first portion of the gate layer and a second portion of the sacrificial layer using a second slurry or etchant having a second selectivity of second material to first material to form a planarized gate layer. The first selectivity is greater than the second selectivity. An example benefit includes reduced dependency of the gate layer planarization process on underlying structure density and reduced variation in thickness of the gate layer on device structures across a wafer.

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