公开(公告)号：US12293917B2

公开(公告)日：2025-05-06

申请号：US17355981

申请日：2021-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Chien Hou ,  Po-Chin Nien ,  Chih Hung Chen ,  Ying-Tsung Chen ,  Kei-Wei Chen

IPC: H01L21/321 ,  B24B37/34 ,  B24B53/017 ,  H01L21/306

Abstract: A chemical mechanical planarization system includes a chemical mechanical planarization pad that rotates during a chemical mechanical planarization process. A chemical mechanical planarization head places a semiconductor wafer in contact with the chemical mechanical planarization pad during the process. A slurry supply system supplies a slurry onto the pad during the process. A pad conditioner conditions the pad during the process. An impurity removal system removes debris and impurities from the slurry.

公开(公告)号：US09922837B2

公开(公告)日：2018-03-20

申请号：US15058956

申请日：2016-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wen Liu ,  Che-Hao Tu ,  Po-Chin Nien ,  William Weilun Hong ,  Ying-Tsung Chen

IPC: H01L21/302 ,  H01L21/306 ,  H01L21/66 ,  H01L23/544 ,  H01L21/67 ,  H01L21/321

CPC classification number: H01L21/30625 ,  B24B37/30 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/67092 ,  H01L22/12 ,  H01L22/26 ,  H01L23/544 ,  H01L2223/54493

Abstract: A method includes measuring a topography of a wafer, determining that a first portion of the wafer has a greater thickness than a specified thickness. The method further includes, after measuring the wafer, performing a Chemical Mechanical Polishing (CMP) process to a first side of the wafer, and during application of the CMP process, applying additional pressure to a region of the wafer, the region comprising an asymmetric part of the wafer, the region including at least a part of the first portion of the wafer.

公开(公告)号：US20170256414A1

公开(公告)日：2017-09-07

申请号：US15058956

申请日：2016-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wen Liu ,  Che-Hao Tu ,  Po-Chin Nien ,  William Weilun Hong ,  Ying-Tsung Chen

IPC: H01L21/306 ,  H01L23/544 ,  H01L21/67 ,  H01L21/66

CPC classification number: H01L21/30625 ,  B24B37/30 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/67092 ,  H01L22/12 ,  H01L22/26 ,  H01L23/544 ,  H01L2223/54493

Abstract: A method includes measuring a topography of a wafer, determining that a first portion of the wafer has a greater thickness than a specified thickness. The method further includes, after measuring the wafer, performing a Chemical Mechanical Polishing (CMP) process to a first side of the wafer, and during application of the CMP process, applying additional pressure to a region of the wafer, the region comprising an asymmetric part of the wafer, the region including at least a part of the first portion of the wafer.

公开(公告)号：US20230154762A1

公开(公告)日：2023-05-18

申请号：US17739783

申请日：2022-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Wei Hu ,  Po-Chin Nien

IPC: H01L21/321 ,  H01L21/768 ,  H01L21/306 ,  H01L21/67 ,  H01L29/66

CPC classification number: H01L21/3212 ,  H01L21/7684 ,  H01L21/30625 ,  H01L21/67092 ,  H01L29/66545

Abstract: A method of forming a semiconductor device is provided. The method includes forming a first film over an active region of a first side of a semiconductor substrate and a second film over a second side of the semiconductor substrate opposing to the first side of the semiconductor substrate; applying a chemical mechanical polishing to remove at least a portion of the second film; after the chemical mechanical polishing, forming a photoresist layer over the first film; and patterning the photoresist layer using an extreme ultraviolet radiation.

公开(公告)号：US10541139B2

公开(公告)日：2020-01-21

申请号：US15079243

申请日：2016-03-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Chin Nien ,  William Weilun Hong ,  Ying-Tsung Chen

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/321 ,  H01L21/3105

Abstract: A method of forming a semiconductor device includes forming fins on a substrate, depositing a gate layer having a first material on the fins, and depositing a sacrificial layer having a second material on the gate layer. The method further includes removing a first portion of the sacrificial layer using a first slurry or etchant having a first selectivity of second material to first material. The method further includes removing a first portion of the gate layer and a second portion of the sacrificial layer using a second slurry or etchant having a second selectivity of second material to first material to form a planarized gate layer. The first selectivity is greater than the second selectivity. An example benefit includes reduced dependency of the gate layer planarization process on underlying structure density and reduced variation in thickness of the gate layer on device structures across a wafer.

公开(公告)号：US20170278712A1

公开(公告)日：2017-09-28

申请号：US15079243

申请日：2016-03-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Po-Chin Nien ,  William Weilun Hong ,  Ying-Tsung Chen

IPC: H01L21/28 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes forming fins on a substrate, depositing a gate layer having a first material on the fins, and depositing a sacrificial layer having a second material on the gate layer. The method further includes removing a first portion of the sacrificial layer using a first slurry or etchant having a first selectivity of second material to first material. The method further includes removing a first portion of the gate layer and a second portion of the sacrificial layer using a second slurry or etchant having a second selectivity of second material to first material to form a planarized gate layer. The first selectivity is greater than the second selectivity. An example benefit includes reduced dependency of the gate layer planarization process on underlying structure density and reduced variation in thickness of the gate layer on device structures across a wafer.