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公开(公告)号：US11940737B2
公开(公告)日：2024-03-26
申请号：US17315087
申请日：2021-05-07
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Hsueh-Yi Chung , Yung-Cheng Chen , Fei-Gwo Tsai , Chi-Hung Liao , Shih-Chi Fu , Wei-Ti Hsu , Jui-Ping Chuang , Tzong-Sheng Chang , Kuei-Shun Chen , Meng-Wei Chen
CPC classification number: G03F7/70433 , G03F1/50 , G03F1/68 , G03F1/70 , G03F1/78 , G03F7/20 , G03F7/70141 , G03F7/70158 , G03F7/70716 , H01L22/30
Abstract: A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.
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公开(公告)号：US10763305B2
公开(公告)日：2020-09-01
申请号：US16134063
申请日：2018-09-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Woan-Yun Hsiao , Huang-Kui Chen , Tzong-Sheng Chang , Ya-Chin King , Chrong-Jung Lin
IPC: H01L27/24 , H01L29/417 , H01L29/78
Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure. In addition, the first conductive structure is in direct contact with the first source/drain structure, and the second conductive structure is not in direct contact with the second source/drain structure.
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公开(公告)号：US10534272B2
公开(公告)日：2020-01-14
申请号：US16127017
申请日：2018-09-10
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Hsueh-Yi Chung , Yung-Cheng Chen , Fei-Gwo Tsai , Chi-Hung Liao , Shih-Chi Fu , Wei-Ti Hsu , Jui-Ping Chuang , Tzong-Sheng Chang , Kuei-Shun Chen , Meng-Wei Chen
Abstract: A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.
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4.发明授权公开(公告)号：US11653503B2
公开(公告)日：2023-05-16
申请号：US16948034
申请日：2020-08-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Woan-Yun Hsiao , Huang-Kui Chen , Tzong-Sheng Chang , Ya-Chin King , Chrong-Jung Lin
IPC: H01L21/82 , H01L27/24 , H01L29/417 , H01L29/78
CPC classification number: H01L27/2436 , H01L29/41725 , H01L29/78
Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure. In addition, the first conductive structure is in direct contact with the first source/drain structure, and the second conductive structure is not in direct contact with the second source/drain structure.
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公开(公告)号：US10090360B2
公开(公告)日：2018-10-02
申请号：US14885035
申请日：2015-10-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Woan-Yun Hsiao , Ya-Chin King , Chrong-Jung Lin , Huang-Kui Chen , Tzong-Sheng Chang
IPC: H01L29/78 , H01L27/24 , H01L29/417
Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure. In addition, the first conductive structure is in direct contact with the first source/drain structure, and the second conductive structure is not in direct contact with the second source/drain structure.
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Patent Agency Ranking
6.发明授权公开(公告)号：US10073354B2
公开(公告)日：2018-09-11
申请号：US14706871
申请日：2015-05-07
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Hsueh-Yi Chung , Yung-Cheng Chen , Fei-Gwo Tsai , Chi-Hung Liao , Shih-Chi Fu , Wei-Ti Hsu , Jui-Ping Chuang , Tzong-Sheng Chang , Kuei-Shun Chen , Meng-Wei Chen
CPC classification number: G03F7/70433 , G03F1/50 , G03F1/68 , G03F1/70 , G03F1/78 , G03F7/20 , G03F7/70141 , G03F7/70158 , G03F7/70716 , H01L22/30
Abstract: A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.
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7.发明授权Apparatus and method for designing an integrated circuit layout having a plurality of cell technologies 有权用于设计具有多个电池技术的集成电路布局的装置和方法公开(公告)号：US09122828B2
公开(公告)日：2015-09-01
申请号：US13896373
申请日：2013-05-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tsung-Yu Chiang , Kuang-Hsin Chen , Song-Bor Lee , Bor-Zen Tien , Tzong-Sheng Chang
IPC: G06F17/50
CPC classification number: G06F17/5072
Abstract: A system and method of designing a layout for a plurality of different logic operation (LOP) cell technologies includes defining a priority for each LOP cell technology in the plurality of different LOP technologies and forming a layout of the plurality of different LOP cells for formation on a substrate with at least some of the LOP cells of higher priority LOP technologies overlapping LOP cells of lower priority LOP technologies. The system can include a processor coupled to memory where stored code defines the priority for each different cell technology in the plurality of LOP cells and (when the code is executed) the processor forms the layout of a plurality of different LOP cells. All of the LOP cells of higher priority LOP technologies overlap LOP cells of lower priority. The system or method also avoids the overlap of higher priority LOP cells by lower priority LOP cells.
Abstract translation: 设计用于多个不同逻辑操作（LOP）单元技术的布局的系统和方法包括为多个不同的LOP技术中的每个LOP单元技术定义优先级，并且形成用于形成的多个不同LOP单元的布局 具有较高优先级LOP技术的至少一些LOP单元的衬底与较低优先级的LOP技术的LOP单元重叠。 该系统可以包括耦合到存储器的处理器，其中存储的代码为多个LOP单元中的每个不同的单元技术定义优先级，并且（当代码被执行时）处理器形成多个不同的LOP单元的布局。 较高优先级的LOP技术的所有LOP单元重叠优先级较低的LOP单元。 该系统或方法还避免了较低优先级的LOP单元与较高优先级的LOP单元的重叠。
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8.发明申请APPARATUS AND METHOD FOR DESIGNING AN INTEGRATED CIRCUIT LAYOUT HAVING A PLURALITY OF CELL TECHNOLOGIES 有权用于设计具有多种细胞技术的集成电路布局的装置和方法公开(公告)号：US20140344770A1
公开(公告)日：2014-11-20
申请号：US13896373
申请日：2013-05-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tsung-Yu CHIANG , Kuang-Hsin Chen , Song-Bor Lee , Bor-Zen Tien , Tzong-Sheng Chang
IPC: G06F17/50
CPC classification number: G06F17/5072
Abstract: A system and method of designing a layout for a plurality of different logic operation (LOP) cell technologies includes defining a priority for each LOP cell technology in the plurality of different LOP technologies and forming a layout of the plurality of different LOP cells for formation on a substrate with at least some of the LOP cells of higher priority LOP technologies overlapping LOP cells of lower priority LOP technologies. The system can include a processor coupled to memory where stored code defines the priority for each different cell technology in the plurality of LOP cells and (when the code is executed) the processor forms the layout of a plurality of different LOP cells. All of the LOP cells of higher priority LOP technologies overlap LOP cells of lower priority. The system or method also avoids the overlap of higher priority LOP cells by lower priority LOP cells.
Abstract translation: 设计用于多个不同逻辑操作（LOP）单元技术的布局的系统和方法包括为多个不同的LOP技术中的每个LOP单元技术定义优先级，并且形成用于形成的多个不同LOP单元的布局 具有较高优先级LOP技术的至少一些LOP单元的衬底与较低优先级的LOP技术的LOP单元重叠。 该系统可以包括耦合到存储器的处理器，其中存储的代码为多个LOP单元中的每个不同的单元技术定义优先级，并且（当代码被执行时）处理器形成多个不同的LOP单元的布局。 较高优先级的LOP技术的所有LOP单元重叠优先级较低的LOP单元。 该系统或方法还避免了较低优先级的LOP单元与较高优先级的LOP单元的重叠。
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公开(公告)号：US11003091B2
公开(公告)日：2021-05-11
申请号：US16740256
申请日：2020-01-10
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Hsueh-Yi Chung , Yung-Cheng Chen , Fei-Gwo Tsai , Chi-Hung Liao , Shih-Chi Fu , Wei-Ti Hsu , Jui-Ping Chuang , Tzong-Sheng Chang , Kuei-Shun Chen , Meng-Wei Chen
Abstract: A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.
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公开(公告)号：US09831130B2
公开(公告)日：2017-11-28
申请号：US15618895
申请日：2017-06-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
Inventor： An-Lun Lo , Wei-Shuo Ho , Tzong-Sheng Chang , Chrong-Jung Lin , Ya-Chin King
IPC: H01L21/76 , H01L21/8234 , H01L29/66 , H01L27/088 , H01L27/112 , H01L29/78 , H01L29/165
CPC classification number: H01L21/823481 , H01L21/76224 , H01L21/76814 , H01L21/76843 , H01L21/76855 , H01L21/76897 , H01L23/5252 , H01L27/088 , H01L27/11206 , H01L29/165 , H01L29/66545 , H01L29/66636 , H01L29/7848
Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack, a second gate stack, and a third gate stack, which are positioned over a semiconductor substrate and spaced apart from each other. The method includes removing portions of the semiconductor substrate to form a first recess, a second recess, and a third recess in the semiconductor substrate. The method includes forming a first doped structure, a second doped structure, and an isolation structure in the first recess, the second recess, and the third recess respectively. The first gate stack, the second gate stack, the first doped structure, and the second doped structure together form a memory cell. The isolation structure is wider and thinner than the second doped structure. A top surface of the isolation structure has a fourth recess.
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