公开(公告)号：US09947766B2

公开(公告)日：2018-04-17

申请号：US15645164

申请日：2017-07-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Yu Chiang ,  Kuang-Hsin Chen

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L21/336 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L29/417 ,  H01L29/786 ,  H01L29/06 ,  H01L21/768 ,  H01L21/3105

CPC classification number: H01L29/66545 ,  H01L21/28008 ,  H01L21/31053 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/41775 ,  H01L29/78 ,  H01L29/78606

Abstract: A semiconductor device includes a substrate, a source/drain region, an etch stop layer, an oxide layer, an interlayer dielectric layer, and a contact plug. The source/drain region is in the substrate. The etch stop layer is over the source/drain region. The oxide layer is over the etch stop layer. The interlayer dielectric layer is over the oxide layer. The contact plug is electrically connected to the source/drain region through the interlayer dielectric layer, the oxide layer, and the etch stop layer.

公开(公告)号：US09711408B2

公开(公告)日：2017-07-18

申请号：US14994603

申请日：2016-01-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Yu Chiang ,  Kuang-Hsin Chen

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823418 ,  H01L21/823437 ,  H01L27/088

Abstract: A method of manufacturing an integrated circuit structure includes forming a plurality of gate stacks on a first area and a second area of a substrate. A photo-resist layer is formed over the gate stacks on the first area. An ion-doped layer is formed in the second area. The photo-resist layer is removed. A first etching recess is formed in the first area and between two gate stacks. A second etching recess is formed in the second area and between two gate stacks. An epitaxial material is filled into the first etching recess and the second etching recess to form a first epitaxial structure and a second epitaxial structure.

公开(公告)号：US09620645B1

公开(公告)日：2017-04-11

申请号：US14871361

申请日：2015-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Cheng-Chieh Lai ,  Kuang-Hsin Chen ,  Yung-Chun Wu ,  Mu-Shih Yeh

IPC: H01L29/16 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/161 ,  H01L29/04 ,  H01L29/66 ,  H01L21/3065

CPC classification number: H01L21/28114 ,  H01L21/3065 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785

Abstract: A FinFET device structure and method for forming the same is provided. The FinFET device structure includes an oxide layer formed over a substrate and a fin structure formed over the oxide layer. The fin structure is made of a semiconductor layer, and the semiconductor layer includes a first portion, a second portion and a third portion. The second portion is between the first portion and the third portion. The first portion, the second portion and the third portion construct a U-shaped trench, and the second portion is below the U-shaped trench. The FinFET device structure further includes a gate structure formed in the U-shaped trench.

公开(公告)号：US09269626B2

公开(公告)日：2016-02-23

申请号：US14174547

申请日：2014-02-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Yu Chiang ,  Kuang-Hsin Chen

IPC: H01L29/76 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823418 ,  H01L21/823437 ,  H01L27/088

Abstract: An integrated circuit structure is provided including a substrate, a low voltage device and a high voltage device. The low voltage device has a first beeline distance from a first epitaxial structure to an adjacent gate stack; and the high voltage structure has a second beeline distance from a second epitaxial structure to an adjacent gate stack. The second beeline distance of the high voltage device is greater than the first beeline distance of the low voltage device, so that the leakage current in the high voltage device may be decreased under high voltage operation. Further, a method for manufacturing the integrated circuit structure also provides herein.

Abstract translation: 提供了一种集成电路结构，包括基板，低压装置和高压装置。 低电压装置具有从第一外延结构到相邻栅极堆叠的第一直线距离; 并且高电压结构具有从第二外延结构到相邻栅极堆叠的第二直线距离。 高压装置的第二直线距离大于低压装置的第一直线距离，使得高压装置中的漏电流可能在高电压操作下降低。 此外，还提供了一种用于制造集成电路结构的方法。

公开(公告)号：US09231067B2

公开(公告)日：2016-01-05

申请号：US14191282

申请日：2014-02-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Yu Chiang ,  Kuang-Hsin Chen

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/417 ,  H01L29/78 ,  H01L21/28 ,  H01L21/768

CPC classification number: H01L29/66545 ,  H01L21/28008 ,  H01L21/31053 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/41775 ,  H01L29/78 ,  H01L29/78606

Abstract: A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, a source/drain regions adjacent to the pair of spacers in the substrate, an etch stop layer next to the gate structure and overlying the substrate, a contact plug extending into the source/drain region and partially overlapping the gate structure, a protective layer over the etch stop layer overlying the substrate and covering the etch stop layer next to the gate structure without the contact plug, and an interlayer dielectric layer over the protective layer. The contact plug has no contact-to-gate short issue to the gate structure.

Abstract translation: 提供半导体器件和制造半导体器件的方法。 半导体器件包括衬底，衬底上的栅极结构，与衬底中的该对间隔物相邻的源极/漏极区域，邻近栅极结构并覆盖衬底的蚀刻停止层，延伸到源极中的接触插塞 /漏极区域并且部分地与栅极结构重叠，覆盖在衬底上的蚀刻停止层上方的保护层，并且覆盖除了接触插塞之外的栅极结构旁边的蚀刻停止层以及保护层上的层间电介质层。 接触插头与栅极结构没有接触到栅极的短路问题。

公开(公告)号：US20150221555A1

公开(公告)日：2015-08-06

申请号：US14174547

申请日：2014-02-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Yu CHIANG ,  Kuang-Hsin Chen

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823418 ,  H01L21/823437 ,  H01L27/088

Abstract: An integrated circuit structure is provided including a substrate, a low voltage device and a high voltage device. The low voltage device has a first beeline distance from a first epitaxial structure to an adjacent gate stack; and the high voltage structure has a second beeline distance from a second epitaxial structure to an adjacent gate stack. The second beeline distance of the high voltage device is greater than the first beeline distance of the low voltage device, so that the leakage current in the high voltage device may be decreased under high voltage operation. Further, a method for manufacturing the integrated circuit structure also provides herein.

Abstract translation: 提供了一种集成电路结构，包括基板，低压装置和高压装置。 低电压装置具有从第一外延结构到相邻栅极堆叠的第一直线距离; 并且高电压结构具有从第二外延结构到相邻栅极堆叠的第二直线距离。 高压装置的第二直线距离大于低压装置的第一直线距离，使得高压装置中的漏电流可能在高电压操作下降低。 此外，还提供了一种用于制造集成电路结构的方法。

公开(公告)号：US10347766B2

公开(公告)日：2019-07-09

申请号：US14475132

申请日：2014-09-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Shuo Ho ,  Chia-Ming Chang ,  Tsung-Yu Chiang ,  Kuang-Hsin Chen ,  Bor-Zen Tien

IPC: H01L21/76 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/02

Abstract: Embodiments of the present disclosure relate generally to a semiconductor device and method of fabricating the same, the semiconductor device includes a semiconductor substrate and a gate stack disposed over a channel region of the semiconductor device, the gate stack includes an oxidation layer, a gate dielectric and a gate electrode, the oxidation layer at least covers a portion of the channel region of the semiconductor device and may act as a barrier to prevent damage to the underlying features, such as the source and drain regions, during removal of a dummy gate in a gate last process.

公开(公告)号：US09842761B2

公开(公告)日：2017-12-12

申请号：US15418269

申请日：2017-01-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Yu Chiang ,  Chung-Wei Lin ,  Kuang-Hsin Chen ,  Bor-Zen Tien

IPC: H01L21/82 ,  H01L21/762 ,  H01L21/263 ,  H01L21/266 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L27/12 ,  H01L21/3115 ,  H01L21/311

CPC classification number: H01L21/76237 ,  H01L21/2636 ,  H01L21/266 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device is provided. The semiconductor device includes a first fin partially surrounded by a first isolation structure and a second fin partially surrounded by a second isolation structure. The second isolation structure has a dopant concentration higher than that of the first isolation structure, and a height difference is between a top surface of the first isolation structure and a top surface of the second isolation structure.

公开(公告)号：US09711611B2

公开(公告)日：2017-07-18

申请号：US15083383

申请日：2016-03-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Yu Chiang ,  Wei-Shuo Ho ,  Kuang-Hsin Chen

IPC: H01L29/49 ,  H01L21/3213 ,  H01L21/321 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L21/768

CPC classification number: H01L29/4966 ,  H01L21/31053 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/32138 ,  H01L21/76897 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor device includes a transistor and a contact pad over a substrate. The transistor includes a high-k dielectric layer, a work function metal layer, a metal gate, two spacers, a metal compound, an insulator and a doped region. The high-k dielectric layer is over the substrate. The work function metal layer is over the high-k dielectric layer. The metal gate is over the work function metal layer. The two spacers sandwich the work function metal layer and the metal gate. The metal compound is over inner walls of the two spacers and over the top surface of the work function metal layer and the metal gate. The insulator covers the metal compound. The doped region is in the substrate. The contact pad is electrically connected to the metal gate.

公开(公告)号：US09704970B2

公开(公告)日：2017-07-11

申请号：US15165293

申请日：2016-05-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Yu Chiang ,  Kuang-Hsin Chen

IPC: H01L21/336 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/768 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/28008 ,  H01L21/31053 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/41775 ,  H01L29/78 ,  H01L29/78606

Abstract: A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, a source/drain regions adjacent to the pair of spacers in the substrate, an etch stop layer next to the gate structure and overlying the substrate, a contact plug extending into the source/drain region and partially overlapping the gate structure, a protective layer over the etch stop layer overlying the substrate and covering the etch stop layer next to the gate structure without the contact plug, and an interlayer dielectric layer over the protective layer. The contact plug has no contact-to-gate short issue to the gate structure.