公开(公告)号：US20250093593A1

公开(公告)日：2025-03-20

申请号：US18403531

申请日：2024-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chih Lin ,  Cheng-Yu Kuo ,  Yen-Hung Chen ,  Hsuan-Ting Kuo ,  Chia-Shen Cheng ,  Chao-Wei Li ,  Ching-Hua Hsieh ,  Wen-Chih Chiou ,  Ming-Fa Chen ,  Shang-Yun Hou

IPC: G02B6/42

Abstract: Optical devices and methods of manufacture are presented in which a mirror structure is utilized to transmit and receive optical signals to and from an optical device. In embodiments the mirror structure receives optical signals from outside of an optical device and directs the optical signals through at least one mirror to an optical component of the optical device.

公开(公告)号：US20240234210A1

公开(公告)日：2024-07-11

申请号：US18151643

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Chun Liao ,  Yen-Hung Chen ,  Ching-Hua Hsieh ,  Sung-Yueh Wu ,  Chih-Wei Lin ,  Kung-Chen Yeh

IPC: H01L21/822 ,  H01L21/3065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L21/822 ,  H01L21/3065 ,  H01L21/56 ,  H01L23/3121 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L2224/08059 ,  H01L2224/08145 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/10156 ,  H01L2924/10157

Abstract: An integrated circuit package including integrated circuit dies and a method of forming are provided. The integrated circuit package may include a first integrated circuit die and a second integrated circuit die bonded to the first integrated circuit die. The first integrated circuit die may include a first substrate, a first interconnect structure, and a first bonding layer. The first interconnect structure may be between the first bonding layer and the first substrate. The second integrated circuit die may include a second substrate, a second interconnect structure, and a second bonding layer. The second interconnect structure may be between the second bonding layer and the second substrate. A first surface of the first bonding layer may be in direct contact with a first surface of the second bonding layer. A sidewall the first bonding layer and the first surface of the second bonding layer may form a first acute angle.

公开(公告)号：US11119416B2

公开(公告)日：2021-09-14

申请号：US16439546

申请日：2019-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Yuan Sun ,  Yen-Liang Chen ,  He Fan ,  Yen-Hung Chen ,  Kai Lin

IPC: G03F7/20

Abstract: A method includes forming a first overlay feature in a first dielectric layer over a first wafer; forming a second dielectric layer over the first overlay feature and the first dielectric layer; forming an opening in the second dielectric layer by at least using an exposure tool; forming a second overlay feature in the opening of the second dielectric layer, such that a first edge of the first overlay feature is covered by the second dielectric layer; directing an electron beam to the first and second overlay features and the second dielectric layer; detecting the electron beam reflected from the first overlay feature through the second dielectric layer and from the second overlay feature by a detector; obtaining, by a controller, an overlay error between the first overlay feature and the second overlay feature according to the reflected electron beam electrically connected to the detector.