公开(公告)号：US09176479B2

公开(公告)日：2015-11-03

申请号：US14161714

申请日：2014-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsieh-Hung Hsieh ,  Yen-Jen Chen ,  Chewn-Pu Jou

IPC: H03M1/50 ,  G04F10/00 ,  H03L7/085 ,  H03K5/159 ,  G04F10/10

CPC classification number: G04F10/005 ,  G04F10/105 ,  H03K5/159 ,  H03L7/085 ,  H03M1/50

Abstract: A time-to-digital converter (TDC) comprises a first delay line including a plurality of first delay cells connected in series, wherein each of the first delay cells include a plurality of first delay units connected in series, wherein each of the first delay units includes a tunable PMOS transistor, a first poly on oxide definition (OD) edge (PODE) transistor, and a pull-up PMOS transistor. The TDC further comprises a second delay line including a plurality of second delay cells connected in series, wherein each of the second delay cells include a plurality of second delay units connected in series, wherein each of the second delay units includes a tunable NMOS transistor, a second PODE transistor, and a pull-down NMOS transistor.

Abstract translation: 时间数字转换器（TDC）包括包括串联连接的多个第一延迟单元的第一延迟线，其中每个第一延迟单元包括串联连接的多个第一延迟单元，其中第一延迟 单元包括可调谐PMOS晶体管，第一多晶氧化物界定（OD）边缘（PODE）晶体管和上拉PMOS晶体管。 TDC还包括包括串联连接的多个第二延迟单元的第二延迟线，其中每个第二延迟单元包括串联连接的多个第二延迟单元，其中每个第二延迟单元包括可调NMOS晶体管， 第二PODE晶体管和下拉式NMOS晶体管。

公开(公告)号：US11079428B2

公开(公告)日：2021-08-03

申请号：US16845515

申请日：2020-04-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsieh-Hung Hsieh ,  Yen-Jen Chen ,  Tzu-Jin Yeh

IPC: G01R31/28

Abstract: A test circuit includes an amplifier configured to receive an AC signal, and output an amplified AC signal based on the AC signal, a first detection circuit configured to generate a first DC voltage having a first value based on an amplitude of the AC signal, and a second detection circuit configured to generate a second DC voltage having a second value based on an amplitude of the amplified AC signal.

公开(公告)号：US20150205267A1

公开(公告)日：2015-07-23

申请号：US14161714

申请日：2014-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsieh-Hung Hsieh ,  Yen-Jen Chen ,  Chewn-Pu Jou

IPC: G04F10/00 ,  H03K5/159 ,  H03L7/085

CPC classification number: G04F10/005 ,  G04F10/105 ,  H03K5/159 ,  H03L7/085 ,  H03M1/50

Abstract: A time-to-digital converter (TDC) comprises a first delay line including a plurality of first delay cells connected in series, wherein each of the first delay cells include a plurality of first delay units connected in series, wherein each of the first delay units includes a tunable PMOS transistor, a first poly on oxide definition (OD) edge (PODE) transistor, and a pull-up PMOS transistor. The TDC further comprises a second delay line including a plurality of second delay cells connected in series, wherein each of the second delay cells include a plurality of second delay units connected in series, wherein each of the second delay units includes a tunable NMOS transistor, a second PODE transistor, and a pull-down NMOS transistor.

Abstract translation: 时间数字转换器（TDC）包括包括串联连接的多个第一延迟单元的第一延迟线，其中每个第一延迟单元包括串联连接的多个第一延迟单元，其中第一延迟 单元包括可调谐PMOS晶体管，第一多晶氧化物界定（OD）边缘（PODE）晶体管和上拉PMOS晶体管。 TDC还包括包括串联连接的多个第二延迟单元的第二延迟线，其中每个第二延迟单元包括串联连接的多个第二延迟单元，其中每个第二延迟单元包括可调NMOS晶体管， 第二PODE晶体管和下拉式NMOS晶体管。

公开(公告)号：US10192833B2

公开(公告)日：2019-01-29

申请号：US14943063

申请日：2015-11-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Feng-Wei Kuo ,  Hui Yu Lee ,  Huan-Neng Chen ,  Yen-Jen Chen ,  Yu-Ling Lin ,  Chewn-Pu Jou

IPC: H01L23/552 ,  H01L23/498 ,  H01L23/66 ,  H01L23/14 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/64 ,  H01L25/065

Abstract: Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.

公开(公告)号：US09219039B2

公开(公告)日：2015-12-22

申请号：US14018634

申请日：2013-09-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Wei Kuo ,  Hui Yu Lee ,  Huan-Neng Chen ,  Yen-Jen Chen ,  Yu-Ling Lin ,  Chewn-Pu Jou

IPC: H01L23/552 ,  H01L23/538 ,  H01L23/14 ,  H01L23/00 ,  H01L25/16 ,  H01L23/498 ,  H01L23/31 ,  H01L23/64 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/642 ,  H01L23/66 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0655 ,  H01L2223/6677 ,  H01L2224/131 ,  H01L2224/14135 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/014

Abstract: Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.

Abstract translation: 插入器和半导体封装实施例提供了隔离和抑制电子噪声，例如半导体封装中的EM发射。 插入器包括各种实施例中的屏蔽结构，屏蔽结构阻挡来自噪声源的电噪声与其它电信号或装置。 在其他实施例中，屏蔽件包括固体结构和一些实施例以及去耦电容器。 耦合结构包括多个包含在条中的焊球，其耦合部件并围绕并包含电噪声源。