公开(公告)号：US10360339B2

公开(公告)日：2019-07-23

申请号：US15043961

申请日：2016-02-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Chun Wang ,  Ching-Hsu Chang ,  Chun-Hung Wu ,  Cheng Kun Tsai ,  Feng-Ju Chang ,  Feng-Lung Lin ,  Ming-Hsuan Wu ,  Ping-Chieh Wu ,  Ru-Gun Liu ,  Wen-Chun Huang ,  Wen-Hao Liu

IPC: G06F17/50 ,  G03F1/00 ,  G03F7/20 ,  G03F1/36 ,  H01L27/02

Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving an IC design layout, wherein the IC design layout includes multiple IC regions and each of the IC regions includes an initial IC pattern. The method further includes performing a correction process to a first IC region, thereby modifying the initial IC pattern in the first IC region to result in a first corrected IC pattern in the first IC region, wherein the correction process includes location effect correction. The method further includes replacing the initial IC pattern in a second IC region with the first corrected IC pattern.

公开(公告)号：US10747938B2

公开(公告)日：2020-08-18

申请号：US16516853

申请日：2019-07-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Chun Wang ,  Ching-Hsu Chang ,  Chun-Hung Wu ,  Cheng Kun Tsai ,  Feng-Ju Chang ,  Feng-Lung Lin ,  Ming-Hsuan Wu ,  Ping-Chieh Wu ,  Ru-Gun Liu ,  Wen-Chun Huang ,  Wen-Hao Liu

IPC: G06F17/50 ,  G06F30/398 ,  G03F7/20 ,  G03F1/36 ,  H01L27/02 ,  G06F30/39 ,  G06F119/18

Abstract: An integrated circuit (IC) manufacturing method includes receiving an IC design layout having IC regions separate from each other. Each of the IC regions includes an initial IC pattern that is substantially identical among the IC regions. The method further includes identifying a group of IC regions from the IC regions. All IC regions in the group have a substantially same location effect, which is introduced by global locations of the IC regions on the IC design layout. The method further includes performing a correction process to a first IC region in the group, modifying the initial IC pattern in the first IC region into a first corrected IC pattern. The correction process includes using a computer program to correct location effect. The method further includes replacing the initial IC pattern in a second IC region in the group with the first corrected IC pattern.

公开(公告)号：US20190340330A1

公开(公告)日：2019-11-07

申请号：US16516853

申请日：2019-07-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Chun Wang ,  Ching-Hsu Chang ,  Chun-Hung Wu ,  Cheng Kun Tsai ,  Feng-Ju Chang ,  Feng-Lung Lin ,  Ming-Hsuan WU ,  Ping-Chieh Wu ,  Ru-Gun Liu ,  Wen-Chun Huang ,  Wen-Hao Liu

IPC: G06F17/50 ,  G03F7/20 ,  G03F1/36

Abstract: An integrated circuit (IC) manufacturing method includes receiving an IC design layout having IC regions separate from each other. Each of the IC regions includes an initial IC pattern that is substantially identical among the IC regions. The method further includes identifying a group of IC regions from the IC regions. All IC regions in the group have a substantially same location effect, which is introduced by global locations of the IC regions on the IC design layout. The method further includes performing a correction process to a first IC region in the group, modifying the initial IC pattern in the first IC region into a first corrected IC pattern. The correction process includes using a computer program to correct location effect. The method further includes replacing the initial IC pattern in a second IC region in the group with the first corrected IC pattern.

公开(公告)号：US09418191B2

公开(公告)日：2016-08-16

申请号：US13886062

申请日：2013-05-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Chun Wang ,  Jeng-Horng Chen ,  Shy-Jay Lin ,  Chia-Ping Chiang ,  Cheng Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

IPC: G03F7/00 ,  G06F17/50 ,  G03F1/00 ,  G03F1/78 ,  H01J37/302 ,  H01J37/317 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/20 ,  H01L21/027

CPC classification number: G06F17/5081 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/144 ,  G03F1/78 ,  G03F7/70283 ,  G03F7/70441 ,  H01J37/3026 ,  H01J37/3174 ,  H01J2237/31769 ,  H01J2237/31771 ,  H01L21/0274 ,  H01L21/0275

Abstract: A method for writing a design to a material using an electron beam includes assigning a first dosage to a first polygonal shape. The first polygonal shape occupies a first virtual layer and includes a first set of pixels. The method also includes simulating a first write operation using the first polygonal shape to create the design, discerning an error in the simulated first write operation, and assigning a second dosage to a second polygonal shape to reduce the error. The second polygonal shape occupies a second virtual layer. The method further includes creating a data structure that includes the first and second polygonal shapes and saving the data structure to a non-transitory computer-readable medium.

公开(公告)号：US09262578B2

公开(公告)日：2016-02-16

申请号：US14293050

申请日：2014-06-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Chun Wang ,  Ching-Hsu Chang ,  Feng-Ju Chang ,  Chun-Hung Wu ,  Ping-Chieh Wu ,  Wen-Hao Liu ,  Ming-Hsuan Wu ,  Feng-Lung Lin ,  Cheng Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

IPC: G06F17/50 ,  G03F7/20 ,  G03F1/36

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F7/70441

Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving a design layout of an IC, wherein the design layout includes a plurality of non-overlapping IC regions and each of the IC regions includes a same initial IC pattern. The method further includes dividing the IC regions into a plurality of groups based on a location effect analysis such that all IC regions in a respective one of the groups are to have substantially same location effect. The method further includes performing a correction to one IC region in each of the groups using a correction model that includes location effect; and copying the corrected IC region to other IC regions in the respective group. The method further includes storing the corrected IC design layout in a tangible computer-readable medium for use by a further IC process stage.

Abstract translation: 提供了一种集成电路（IC）制造方法。 该方法包括接收IC的设计布局，其中设计布局包括多个不重叠的IC区域，并且每个IC区域包括相同的初始IC图案。 该方法还包括基于位置效应分析将IC区域分成多个组，使得相应组中的所有IC区域具有基本上相同的位置效果。 该方法还包括使用包括位置效应的校正模型对每个组中的一个IC区域进行校正; 并将校正后的IC区域复制到各组的其他IC区域。 该方法还包括将经修正的IC设计布局存储在有形的计算机可读介质中以供另外的IC处理级使用。

公开(公告)号：US09390217B2

公开(公告)日：2016-07-12

申请号：US14143677

申请日：2013-12-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Chun Wang ,  Ming-Hui Chih ,  Yu-Po Tang ,  Chia-Ping Chiang ,  Feng-Ju Chang ,  Cheng Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

IPC: G06F17/50 ,  G03F1/36 ,  G03F1/70

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/70

Abstract: A method for performing optical proximity correction (OPC) and evaluating OPC solutions is disclosed. An exemplary method includes receiving a design database corresponding to an IC circuit mask. A first OPC modification to a mask feature of the design database is made by performing a first OPC process. The OPC process includes: dividing the mask feature into child shapes and adjusting an attribute of a child shape based on an edge placement error (EPE) factor. A first lithography simulation is performed utilizing a first set of performance indexes after making the first OPC modification, and a second OPC modification to the mask feature is made based on a result of the first lithography simulation. A second lithography simulation of the mask feature is performed utilizing a second set of performance indexes to verify the first and second OPC modifications, and the design database is provided for manufacturing.

Abstract translation: 公开了一种执行光学邻近校正（OPC）和评估OPC解决方案的方法。 一种示例性方法包括接收对应于IC电路掩码的设计数据库。 通过执行第一个OPC过程来对设计数据库的掩码特征进行第一个OPC修改。 OPC过程包括：基于边缘放置误差（EPE）因子将掩模特征划分为子形状并调整子形状的属性。 在进行第一OPC修改之后，利用第一组性能指标执行第一光刻模拟，并且基于第一光刻模拟的结果对掩模特征进行第二OPC修改。 使用第二组性能指标来执行掩模特征的第二光刻仿真以验证第一和第二OPC修改，并且为设计数据库提供制造。

公开(公告)号：US20140109026A1

公开(公告)日：2014-04-17

申请号：US14143677

申请日：2013-12-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Chun Wang ,  Ming-Hui Chih ,  Yu-Po Tang ,  Chia-Ping Chiang ,  Feng-Ju Chang ,  Cheng Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/70

Abstract: A method for performing optical proximity correction (OPC) and evaluating OPC solutions is disclosed. An exemplary method includes receiving a design database corresponding to an IC circuit mask. A first OPC modification to a mask feature of the design database is made by performing a first OPC process. The OPC process includes: dividing the mask feature into child shapes and adjusting an attribute of a child shape based on an edge placement error (EPE) factor. A first lithography simulation is performed utilizing a first set of performance indexes after making the first OPC modification, and a second OPC modification to the mask feature is made based on a result of the first lithography simulation. A second lithography simulation of the mask feature is performed utilizing a second set of performance indexes to verify the first and second OPC modifications, and the design database is provided for manufacturing.

Abstract translation: 公开了一种执行光学邻近校正（OPC）和评估OPC解决方案的方法。 一种示例性方法包括接收对应于IC电路掩码的设计数据库。 通过执行第一个OPC过程来对设计数据库的掩码特征进行第一个OPC修改。 OPC过程包括：基于边缘放置误差（EPE）因子将掩模特征划分为子形状并调整子形状的属性。 在进行第一OPC修改之后，利用第一组性能指标执行第一光刻模拟，并且基于第一光刻模拟的结果对掩模特征进行第二OPC修改。 使用第二组性能指标来执行掩模特征的第二光刻仿真以验证第一和第二OPC修改，并且为设计数据库提供制造。

公开(公告)号：US20160162627A1

公开(公告)日：2016-06-09

申请号：US15043961

申请日：2016-02-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Chun Wang ,  Ching-Hsu Chang ,  Chun-Hung Wu ,  Cheng Kun Tsai ,  Feng-Ju Chang ,  Feng-Lung Lin ,  Ming-Hsuan WU ,  Ping-Chieh Wu ,  Ru-Gun Liu ,  Wen-Chun Huang ,  Wen-Hao Liu

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F7/70441 ,  G06F17/5068 ,  G06F2217/12 ,  H01L27/0207

Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving an IC design layout, wherein the IC design layout includes multiple IC regions and each of the IC regions includes an initial IC pattern. The method further includes performing a correction process to a first IC region, thereby modifying the initial IC pattern in the first IC region to result in a first corrected IC pattern in the first IC region, wherein the correction process includes location effect correction. The method further includes replacing the initial IC pattern in a second IC region with the first corrected IC pattern.

Abstract translation: 提供了一种集成电路（IC）制造方法。 该方法包括接收IC设计布局，其中IC设计布局包括多个IC区域，并且每个IC区域包括初始IC图案。 该方法还包括对第一IC区域执行校正处理，从而修改第一IC区域中的初始IC图案，以产生第一IC区域中的第一校正IC图案，其中校正处理包括位置效果校正。 该方法还包括用第一校正IC图案替换第二IC区域中的初始IC图案。

公开(公告)号：US20150310158A1

公开(公告)日：2015-10-29

申请号：US14293050

申请日：2014-06-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Chun Wang ,  Ching-Hsu Chang ,  Feng-Ju Chang ,  Chun-Hung Wu ,  Ping-Chieh Wu ,  Wen-Hao Liu ,  Ming-Hsuan Wu ,  Feng-Lung Lin ,  Cheng Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F7/70441

Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving a design layout of an IC, wherein the design layout includes a plurality of non-overlapping IC regions and each of the IC regions includes a same initial IC pattern. The method further includes dividing the IC regions into a plurality of groups based on a location effect analysis such that all IC regions in a respective one of the groups are to have substantially same location effect. The method further includes performing a correction to one IC region in each of the groups using a correction model that includes location effect; and copying the corrected IC region to other IC regions in the respective group. The method further includes storing the corrected IC design layout in a tangible computer-readable medium for use by a further IC process stage.

Abstract translation: 提供了一种集成电路（IC）制造方法。 该方法包括接收IC的设计布局，其中设计布局包括多个不重叠的IC区域，并且每个IC区域包括相同的初始IC图案。 该方法还包括基于位置效应分析将IC区域分成多个组，使得相应组中的所有IC区域具有基本上相同的位置效果。 该方法还包括使用包括位置效应的校正模型对每个组中的一个IC区域进行校正; 并将校正后的IC区域复制到各组的其他IC区域。 该方法还包括将经修正的IC设计布局存储在有形的计算机可读介质中以供另外的IC处理级使用。

公开(公告)号：US20140033144A1

公开(公告)日：2014-01-30

申请号：US13886062

申请日：2013-05-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Chun Wang ,  Jeng-Horng Chen ,  Shy-Jay Lin ,  Chia-Ping Chiang ,  Cheng Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/144 ,  G03F1/78 ,  G03F7/70283 ,  G03F7/70441 ,  H01J37/3026 ,  H01J37/3174 ,  H01J2237/31769 ,  H01J2237/31771 ,  H01L21/0274 ,  H01L21/0275

Abstract: A method for writing a design to a material using an electron beam includes assigning a first dosage to a first polygonal shape. The first polygonal shape occupies a first virtual layer and includes a first set of pixels. The method also includes simulating a first write operation using the first polygonal shape to create the design, discerning an error in the simulated first write operation, and assigning a second dosage to a second polygonal shape to reduce the error. The second polygonal shape occupies a second virtual layer. The method further includes creating a data structure that includes the first and second polygonal shapes and saving the data structure to a non-transitory computer-readable medium.

Abstract translation: 使用电子束将设计写入材料的方法包括将第一剂量分配给第一多边形形状。 第一多边形形状占据第一虚拟层并且包括第一组像素。 该方法还包括使用第一多边形形状来模拟第一写入操作以创建设计，识别模拟的第一写入操作中的错误，以及将第二剂量分配给第二多边形形状以减少误差。 第二多边形形状占据第二虚拟层。 该方法还包括创建包括第一和第二多边形形状并将数据结构保存到非暂时性计算机可读介质的数据结构。