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    DIFFUSION BARRIER LAYER FOR CONDUCTIVE VIA TO DECREASE CONTACT RESISTANCE
    2.
    发明申请
    DIFFUSION BARRIER LAYER FOR CONDUCTIVE VIA TO DECREASE CONTACT RESISTANCE 有权

    公开(公告)号：US20220310526A1

    公开(公告)日：2022-09-29

    申请号：US17834148

    申请日：2022-06-07

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Hsiu-Wen Hsueh ,  Chii-Ping Chen ,  Neng-Jye Yang ,  Ya-Lien Lee ,  An-Jiao Fu ,  Ya-Ching Tseng

    IPC分类号： H01L23/532 ,  H01L23/528

    摘要： Some embodiments relate to a semiconductor structure including a method for forming a semiconductor structure. The method includes forming a lower conductive structure within a first dielectric layer over a substrate. An upper dielectric structure is formed over the lower conductive structure. The upper dielectric structure comprises sidewalls defining an opening over the lower conductive structure. A first liner layer is selectively deposited along the sidewalls of the upper dielectric structure. A conductive body is formed within the opening and over the lower conductive structure. The conductive body has a bottom surface directly overlying a middle region of the lower conductive structure. The first layer is laterally offset from the middle region of the lower conductive structure by a non-zero distance.

    INTER-WIRE CAVITY FOR LOW CAPACITANCE
    4.
    发明申请
    INTER-WIRE CAVITY FOR LOW CAPACITANCE 有权

    公开(公告)号：US20220359266A1

    公开(公告)日：2022-11-10

    申请号：US17873381

    申请日：2022-07-26

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Hsiu-Wen Hsueh ,  Jiing-Feng Yang ,  Chii-Ping Chen ,  Po-Hsiang Huang ,  Chang-Wen Chen ,  Cai-Ling Wu

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48

    摘要： Various embodiments of the present disclosure are directed towards an integrated circuit (IC) in which cavities separate wires of an interconnect structure. For example, a conductive feature overlies a substrate, and an intermetal dielectric (IMD) layer overlies the conductive feature. A first wire and a second wire neighbor in the IMD layer and respectively have a first sidewall and a second sidewall that face each other while being separated from each other by the IMD layer. Further, the first wire overlies and borders the conductive feature. A first cavity and a second cavity further separate the first and second sidewalls from each other. The first cavity separates the first sidewall from the IMD layer, and the second cavity separates the second sidewall from the IMD layer. The cavities reduce parasitic capacitance between the first and second wires and hence resistance-capacitance (RC) delay that degrades IC performance.

    THERMAL SENSOR DEVICE BY BACK END OF LINE METAL RESISTOR
    5.
    发明公开
    THERMAL SENSOR DEVICE BY BACK END OF LINE METAL RESISTOR 审中-公开

    公开(公告)号：US20240249991A1

    公开(公告)日：2024-07-25

    申请号：US18156779

    申请日：2023-01-19

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yu-Hsiang Chen ,  Hsiu-Wen Hsueh ,  Szu-Lin Liu ,  Wen-Sheh Huang ,  Chloe Hsin-Yi Chen ,  Wei-Lin Lai

    IPC分类号： H01L23/34 ,  H01L23/522 ,  H01L23/528

    CPC分类号： H01L23/34 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/5283

    摘要： A semiconductor structure includes a substrate having a front side and a back side, one or more dielectric layers over the front side, and a conductive structure. The one or more dielectric layers include a thermal sensor region and two dummy regions sandwiching the thermal sensor region along a second direction from a top view. The thermal sensor region and the two dummy regions extend longitudinally along a first direction generally perpendicular to the second direction from the top view. The conductive structure is embedded in the thermal sensor region of the one or more dielectric layers. The conductive structure includes conductive lines parallel to each other and extending longitudinally along the first direction, and conductive bars and vias electrically connecting the conductive lines. The conductive lines in a same dielectric layer of the one or more dielectric layers are electrically connected one by one zigzaggedly from the top view.

    Forming Interconnect Structures in Semiconductor Devices
    7.
    发明申请
    Forming Interconnect Structures in Semiconductor Devices 有权

    公开(公告)号：US20230060269A1

    公开(公告)日：2023-03-02

    申请号：US17460764

    申请日：2021-08-30

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Hsiu-Wen Hsueh ,  Cai-Ling Wu ,  Chii-Ping Chen ,  Chien-Chih Chiu

    IPC分类号： H01L21/768 ,  H01L23/522

    摘要： A method includes forming a first conductive feature over a substrate, forming an etch-stop layer (ESL) stack over the first conductive feature, forming a first interlayer dielectric (ILD) layer over the ESL stack, forming a patterned ESL having a first opening over the first ILD layer, forming a second ILD layer over the patterned ESL, thereby filling the first opening, forming a patterned HM having a second opening over the second ILD layer, where a width of the second opening is greater than a width of the first opening, performing an etching process to form a first trench in the second ILD layer and a second trench in the first ILD layer, where the second trench exposes the first conductive feature, and subsequently depositing a conductive layer in the first trench and the second trench, thereby forming a second conductive feature interconnecting a third conductive to the first conductive feature.

    ONE-TIME-PROGRAMMABLE DEVICE STRUCTURE
    9.
    发明公开
    ONE-TIME-PROGRAMMABLE DEVICE STRUCTURE 审中-公开

    公开(公告)号：US20230307356A1

    公开(公告)日：2023-09-28

    申请号：US17703710

    申请日：2022-03-24

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yu-Hsiang Chen ,  Wen-Sheh Huang ,  Po-Hsiang Huang ,  Hsiu-Wen Hsueh

    IPC分类号： H01L23/525

    CPC分类号： H01L23/5252

    摘要： a first dielectric layer, a first conductive feature and a second conductive feature in the first dielectric layer, a first dielectric feature disposed directly on the first conductive feature; a first etch stop layer (ESL) disposed over the first dielectric layer and the second conductive feature, a first conductive layer disposed on and in contact with the first dielectric feature, a second ESL disposed over the first conductive layer, a second dielectric layer disposed directly on the first ESL and the second ESL, a first via extending through the second dielectric layer and the second ESL to contact with the first conductive feature, and a second via extending through the second dielectric layer and the first ESL to contact with the second conductive feature.