利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

25 条记录 (耗时 0.019 秒)

    METHOD OF FORMING SEMICONDUCTOR DEVICE INCLUDING SILICIDE LAYERS
    1.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR DEVICE INCLUDING SILICIDE LAYERS 有权
    形成二氧化硅层的半导体器件的方法

    公开(公告)号：US20140179077A1

    公开(公告)日：2014-06-26

    申请号：US14192742

    申请日：2014-02-27

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Hung-Ming Chen ,  Chih-Hao Chang ,  Chih-Hao Yu

    IPC分类号： H01L29/66

    CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L29/401 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7845

    摘要： A method includes forming a gate structure on a semiconductor material region, wherein the gate structure includes spacer elements abutting a gate electrode layer. The gate electrode layer is etched to provide a recess. A hard mask layer is formed over the gate electrode layer in the recess. Silicide layers are then formed on a source region and a drain region disposed in the semiconductor material region, while the hard mask is disposed over the gate electrode layer. A source contact and a drain contact is then provided, each source and drain contact being conductively coupled to a respective one of the silicide layers.

    摘要翻译： 一种方法包括在半导体材料区域上形成栅极结构，其中栅极结构包括邻接栅电极层的隔离元件。 蚀刻栅电极层以提供凹陷。 在凹部中的栅电极层上形成硬掩模层。 然后在设置在半导体材料区域中的源极区域和漏极区域上形成硅化物层，同时将硬掩模设置在栅电极层上。 然后提供源极接触和漏极接触，每个源极和漏极接触导电耦合到相应的一个硅化物层。

    Method of forming semiconductor device including silicide layers
    3.
    发明授权
    Method of forming semiconductor device including silicide layers 有权
    形成包括硅化物层的半导体器件的方法

    公开(公告)号：US09214558B2

    公开(公告)日：2015-12-15

    申请号：US14192742

    申请日：2014-02-27

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Hung-Ming Chen ,  Chih-Hao Chang ,  Chih-Hao Yu

    IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/40 ,  H01L29/49 ,  H01L29/51

    CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L29/401 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7845

    摘要： A method includes forming a gate structure on a semiconductor material region, wherein the gate structure includes spacer elements abutting a gate electrode layer. The gate electrode layer is etched to provide a recess. A hard mask layer is formed over the gate electrode layer in the recess. Silicide layers are then formed on a source region and a drain region disposed in the semiconductor material region, while the hard mask is disposed over the gate electrode layer. A source contact and a drain contact is then provided, each source and drain contact being conductively coupled to a respective one of the silicide layers.

    摘要翻译： 一种方法包括在半导体材料区域上形成栅极结构，其中栅极结构包括邻接栅电极层的隔离元件。 蚀刻栅电极层以提供凹陷。 在凹部中的栅电极层上形成硬掩模层。 然后在设置在半导体材料区域中的源极区域和漏极区域上形成硅化物层，同时将硬掩模设置在栅电极层上。 然后提供源极接触和漏极接触，每个源极和漏极接触导电耦合到相应的一个硅化物层。

    Fin field effect transistor
    4.
    发明授权
    Fin field effect transistor 有权
    鳍场效应晶体管

    公开(公告)号：US09209300B2

    公开(公告)日：2015-12-08

    申请号：US14337494

    申请日：2014-07-22

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Hung-Ta Lin ,  Chu-Yun Fu ,  Shin-Yeh Huang ,  Shu-Tine Yang ,  Hung-Ming Chen

    IPC分类号： H01L29/84 ,  H01L29/78 ,  H01L29/66

    CPC分类号： H01L27/0886 ,  H01L21/02293 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7855

    摘要： A fin field effect transistor including a first insulation region and a second insulation region over a top surface of a substrate. The first insulation region includes tapered top surfaces, and the second insulation region includes tapered top surfaces. The fin field effect transistor further includes a fin extending above the top surface between the first insulation region and the second insulation region. The fin includes a first portion having a top surface below the tapered top surfaces of the first insulation region. The fin includes a second portion having a top surface above the tapered top surfaces of the first insulation region.

    摘要翻译： 一种鳍状场效应晶体管，包括在衬底顶表面上的第一绝缘区域和第二绝缘区域。 第一绝缘区域包括锥形顶表面，并且第二绝缘区域包括锥形顶表面。 翅片场效应晶体管还包括在第一绝缘区域和第二绝缘区域之间的顶表面上方延伸的鳍片。 翅片包括在第一绝缘区域的锥形顶表面下方具有顶表面的第一部分。 翅片包括在第一绝缘区域的锥形顶表面上方具有顶表面的第二部分。

    Fin held effect transistor
    6.
    发明授权
    Fin held effect transistor 有权
    鳍保持效应晶体管

    公开(公告)号：US08809940B2

    公开(公告)日：2014-08-19

    申请号：US13859505

    申请日：2013-04-09

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Hung-Ta Lin ,  Chu-Yun Fu ,  Shin-Yeh Huang ,  Shu-Tine Yang ,  Hung-Ming Chen

    IPC分类号： H01L21/02

    CPC分类号： H01L27/0886 ,  H01L21/02293 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7855

    摘要： A FinFET is described, the FinFET includes a substrate including a top surface and a first insulation region and a second insulation region over the substrate top surface comprising tapered top surfaces. The FinFET further includes a fin of the substrate extending above the substrate top surface between the first and second insulation regions, wherein the fin includes a recessed portion having a top surface lower than the tapered top surfaces of the first and second insulation regions, wherein the fin includes a non-recessed portion having a top surface higher than the tapered top surfaces. The FinFET further includes a gate stack over the non-recessed portion of the fin.

    摘要翻译： 描述了FinFET，FinFET包括包括顶表面和第一绝缘区域的衬底以及包括锥形顶表面的衬底顶表面上的第二绝缘区域。 FinFET还包括在第一和第二绝缘区域之间的衬底顶表面上延伸的衬底的翅片，其中鳍片包括具有比第一和第二绝缘区域的锥形顶表面低的顶表面的凹陷部分，其中 翅片包括具有高于锥形顶表面的顶表面的非凹陷部分。 FinFET还包括在鳍的非凹陷部分上方的栅极堆叠。

    Forming Inter-Device STI Regions and Intra-Device STI Regions Using Different Dielectric Materials
    7.
    发明申请
    Forming Inter-Device STI Regions and Intra-Device STI Regions Using Different Dielectric Materials 有权
    使用不同介质材料形成器件间STI区域和器件内STI区域

    公开(公告)号：US20140004682A1

    公开(公告)日：2014-01-02

    申请号：US14019338

    申请日：2013-09-05

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Feng Yuan ,  Tsung-Lin Lee ,  Hung-Ming Chen ,  Chang-Yun Chang

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211

    摘要： An integrated circuit structure includes a substrate having a first portion in a first device region and a second portion in a second device region; and two insulation regions in the first device region and over the substrate. The two insulation regions include a first dielectric material having a first k value. A semiconductor strip is between and adjoining the two insulation regions, with a top portion of the semiconductor strip forming a semiconductor fin over top surfaces of the two insulation regions. An additional insulation region is in the second device region and over the substrate. The additional insulation region includes a second dielectric material having a second k value greater than the first k value.

    摘要翻译： 集成电路结构包括具有第一器件区域中的第一部分和第二器件区域中的第二部分的衬底; 以及在第一器件区域和衬底上的两个绝缘区域。 两个绝缘区域包括具有第一k值的第一电介质材料。 半导体条在两个绝缘区之间并相邻，半导体条的顶部在两个绝缘区的顶表面上形成半导体鳍。 另外的绝缘区域位于第二器件区域和衬底之上。 附加绝缘区域包括具有大于第一k值的第二k值的第二电介质材料。

    Silicide formation and associated devices
    10.
    发明授权
    Silicide formation and associated devices 有权
    硅化物形成和相关设备

    公开(公告)号：US08623721B2

    公开(公告)日：2014-01-07

    申请号：US13919639

    申请日：2013-06-17

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Hung-Ming Chen ,  Chih-Hao Chang ,  Chih-Hao Yu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L29/401 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7845

    摘要： Improved silicide formation and associated devices are disclosed. An exemplary method includes providing a semiconductor material having spaced source and drain regions therein, forming a gate structure interposed between the source and drain regions, performing a gate replacement process on the gate structure to form a metal gate electrode therein, forming a hard mask layer over the metal gate electrode, forming silicide layers on the respective source and drain regions in the semiconductor material, removing the hard mask layer to expose the metal gate electrode, and forming source and drain contacts, each source and drain contact being conductively coupled to a respective one of the silicide layers.

    摘要翻译： 公开了改进的硅化物形成和相关装置。 一种示例性方法包括提供其间具有间隔的源极和漏极区域的半导体材料，形成插入在源极和漏极区域之间的栅极结构，在栅极结构上执行栅极替换处理以在其中形成金属栅电极，形成硬掩模层 在所述金属栅极电极上，在所述半导体材料中的相应源极和漏极区域上形成硅化物层，去除所述硬掩模层以暴露所述金属栅电极，以及形成源极和漏极接触，每个源极和漏极接触导电耦合到 相应的一个硅化物层。