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公开(公告)号：US12066484B2
公开(公告)日：2024-08-20
申请号：US18359906
申请日：2023-07-27
发明人： Jun He , Yu-Ting Lin , Wei-Hsun Lin , Yung-Liang Kuo , Yinlung Lu
CPC分类号： G01R31/2879 , G01R31/2642 , G01R31/2886
摘要： The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.
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公开(公告)号：US12025655B2
公开(公告)日：2024-07-02
申请号：US18301274
申请日：2023-04-17
发明人： Jun He , Yu-Ting Lin , Wei-Hsun Lin , Yung-Liang Kuo , Yinlung Lu
IPC分类号： G01R31/28
CPC分类号： G01R31/2879 , G01R31/2886
摘要： The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.
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公开(公告)号：US11924965B2
公开(公告)日：2024-03-05
申请号：US17728758
申请日：2022-04-25
发明人： Chun-Wei Chang , Jian-Hong Lin , Shu-Yuan Ku , Wei-Cheng Liu , Yinlung Lu , Jun He
CPC分类号： H05K1/0242 , H05K1/0251 , H05K1/116 , H05K3/427 , H05K3/429 , H05K2201/0776
摘要： A package component and forming method thereof are provided. The package component includes a substrate and a conductive layer. The substrate includes a first surface. The conductive layer is disposed over the first surface. The conductive layer includes a first conductive feature and a second conductive feature. The second conductive feature covers a portion of the first conductive feature. A resistance of the second conductive feature is lower than a resistance of the first conductive feature.
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公开(公告)号：US20240030168A1
公开(公告)日：2024-01-25
申请号：US17814525
申请日：2022-07-24
发明人： Wei-Yu Chen , Hua-Wei Tseng , Li-Hsien Huang , Yinlung Lu , Jun He
IPC分类号： H01L23/00 , H01L25/065 , H01L23/48
CPC分类号： H01L24/08 , H01L24/94 , H01L24/80 , H01L25/0657 , H01L23/481 , H01L2225/06524 , H01L2225/06593 , H01L2924/35121 , H01L2924/30205 , H01L2224/08145 , H01L2224/80908 , H01L2224/80896 , H01L2224/80895 , H01L2224/8011
摘要： A package structure is provided. The package structure includes a bottom die and a top die. The bottom die includes: a first active region surrounded by a first seal ring region; a first seal ring region including a bottom seal ring; and a first bonding layer disposed on a front side of the bottom die. The top die includes: a second active region surrounded by a second seal ring region; a second seal ring region including a top seal ring; and a second bonding layer disposed on a front side of the top die. The bottom die and the top die are bonded through hybrid bonding between the first bonding layer and the second bonding layer at an interface therebetween such that the bottom seal ring and the top seal ring are vertically aligned and are operable to form a continuous seal ring.
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公开(公告)号：US20240063099A1
公开(公告)日：2024-02-22
申请号：US17889122
申请日：2022-08-16
发明人： Ting-Ting Kuo , Li-Hsien Huang , Tien-Chung Yang , Yao-Chun Chuang , Yinlung Lu , Jun He
IPC分类号： H01L23/498 , H01L21/48 , H01L21/56
CPC分类号： H01L23/49822 , H01L23/49894 , H01L21/4857 , H01L21/56
摘要： The present disclosure provides methods and structures to prevent cracks in redistribution layers. A redistribution structure according to the present disclosure includes a first polymer layer disposed over a silicon substrate, a first contact via disposed in the first polymer layer, a second polymer layer disposed over the first contact via, a first redistribution layer including a first conductive pad disposed on the second polymer layer and a second contact via extending through the second polymer layer to physical contact the first contact via, a third polymer layer disposed over the first redistribution layer, a second redistribution layer including a second conductive pad disposed on the third polymer layer and a plurality of third contact vias extending through the third polymer layer to physically contact the first conductive pad. The first conductive pad has at least one opening and the second conductive pad has at least one opening.
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公开(公告)号：US11754621B2
公开(公告)日：2023-09-12
申请号：US17809577
申请日：2022-06-29
发明人： Jun He , Yu-Ting Lin , Wei-Hsun Lin , Yung-Liang Kuo , Yinlung Lu
CPC分类号： G01R31/2879 , G01R31/2642 , G01R31/2886
摘要： The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.
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公开(公告)号：US20240038701A1
公开(公告)日：2024-02-01
申请号：US17814836
申请日：2022-07-26
发明人： Ting-Ting Kuo , Li-Hsien Huang , Tien-Chung Yang , Yao-Chun Chuang , Yinlung Lu , Jun He
IPC分类号： H01L23/00 , H01L23/538 , H01L23/498 , H01L23/31 , H01L23/528 , H01L23/522
CPC分类号： H01L24/08 , H01L23/5389 , H01L23/49816 , H01L23/3128 , H01L23/5286 , H01L23/5226 , H01L24/14 , H01L24/19 , H01L24/73 , H01L2224/12105 , H01L2924/15311 , H01L2224/02379
摘要： A semiconductor package structure is provided. The semiconductor package structure includes: a die having a frontside and a backside; a first redistribution layer (RDL) structure disposed on the backside of the die; a second RDL structure disposed on and electrically connected to the frontside of the die; a through integrated fan-out via (TIV) disposed lateral to the die and extending to electrically connect the first and the second RDL structures; a molding compound disposed between the first and second RDL structures; an enhancement layer disposed on the second RDL structure; a plurality of pre-solder bumps; and a plurality of solder balls disposed on and electrically connected to the second RDL structure. The enhancement layer includes a plurality of cascaded openings electrically connected to the first RDL structure. Each of the pre-solder bumps is disposed in one of the cascaded openings.
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公开(公告)号：US11630149B2
公开(公告)日：2023-04-18
申请号：US17353543
申请日：2021-06-21
发明人： Jun He , Yu-Ting Lin , Wei-Hsun Lin , Yung-Liang Kuo , Yinlung Lu
IPC分类号： G01R31/28
摘要： The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.
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公开(公告)号：US11448692B2
公开(公告)日：2022-09-20
申请号：US17198764
申请日：2021-03-11
发明人： Jun He , Yu-Ting Lin , Wei-Hsun Lin , Yung-Liang Kuo , Yinlung Lu
摘要： The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.
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公开(公告)号：US11073551B2
公开(公告)日：2021-07-27
申请号：US16522551
申请日：2019-07-25
发明人： Jun He , Yu-Ting Lin , Wei-Hsun Lin , Yung-Liang Kuo , Yinlung Lu
IPC分类号： G01R31/28
摘要： The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.
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