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公开(公告)号:US12002721B2
公开(公告)日:2024-06-04
申请号:US17874326
申请日:2022-07-27
发明人: Kuan-Yu Huang , Sung-Hui Huang , Shang-Yun Hou , Chien-Yuan Huang
IPC分类号: H01L25/065 , H01L21/52 , H01L23/04 , H01L23/31 , H01L23/538
CPC分类号: H01L23/04 , H01L21/52 , H01L23/3121 , H01L23/538 , H01L25/0655
摘要: A method of fabricating a semiconductor structure includes providing a first substrate comprising a first side and a second side opposite to the first side. A package is attached to the first side of the first substrate. A second substrate is attached to the second side of the first substrate. A plurality of electrical connectors is bonded between the second side of the first substrate and the second substrate. A lid is attached to the first substrate and the second substrate. The lid includes a ring part and a plurality of overhang parts. The ring part is over the first side of the first substrate. The plurality of overhang parts extends from corner sidewalls of the ring part toward the second substrate. The plurality of overhang parts are laterally aside the plurality of electrical connectors.
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公开(公告)号:US20230307382A1
公开(公告)日:2023-09-28
申请号:US18327076
申请日:2023-06-01
发明人: Kuan-Yu Huang , Sung-Hui Huang , Shang-Yun Hou
IPC分类号: H01L23/00 , H01L21/56 , H01L21/78 , H01L23/31 , H01L23/48 , H01L25/065 , H01L25/00 , H01L23/498
CPC分类号: H01L23/562 , H01L21/561 , H01L21/78 , H01L23/3128 , H01L23/481 , H01L23/49816 , H01L23/49827 , H01L25/0652 , H01L25/0657 , H01L25/50
摘要: A semiconductor device including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a warpage control pattern is provided. The first semiconductor die includes an active surface and a rear surface opposite to the active surface. The second semiconductor die is disposed on the active surface of the first semiconductor die. The insulating encapsulation is disposed on the active surface of the first semiconductor die and laterally encapsulates the second semiconductor die. The warpage control pattern is disposed on and partially covers the rear surface of the first semiconductor die.
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公开(公告)号:US11764123B2
公开(公告)日:2023-09-19
申请号:US17857166
申请日:2022-07-04
发明人: Sung-Hui Huang , Shang-Yun Hou , Tien-Yu Huang , Heh-Chang Huang , Kuan-Yu Huang , Shu-Chia Hsu , Yu-Shun Lin
CPC分类号: H01L23/3185 , H01L25/167
摘要: A semiconductor package includes a substrate, a stacked structure, an encapsulation material, a lid structure, and a coupler. The stacked structure is disposed over and bonded to the substrate. The encapsulation material partially encapsulates the stacked structure. The lid structure is disposed on the substrate, wherein the lid structure surrounds the stacked structure and covers a top surface of the stacked structure. The coupler is bonded to the stacked structure, wherein a portion of the coupler penetrates through and extends out of the lid structure.
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公开(公告)号:US11630271B2
公开(公告)日:2023-04-18
申请号:US17873992
申请日:2022-07-26
发明人: Sung-Hui Huang , Jui-Hsieh Lai , Shang-Yun Hou
摘要: A package structure is provided. The package structure includes a waveguide, a passivation layer, and a reflector. The waveguide is over a substrate. The passivation layer is over the substrate and covers the waveguide. The reflector includes a metal layer and a semiconductor layer on the passivation layer. The metal layer and the first semiconductor layer are in contact with the passivation layer.
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公开(公告)号:US20220336416A1
公开(公告)日:2022-10-20
申请号:US17853949
申请日:2022-06-30
发明人: Wen-Wei Shen , Sung-Hui Huang , Shang-Yun Hou
IPC分类号: H01L25/065 , H01L23/538 , H01L23/31 , H01L21/56
摘要: A package structure includes a circuit substrate and a semiconductor device. The semiconductor device is disposed on and electrically connected to the circuit substrate. The semiconductor device includes an interconnection structure, a semiconductor die, an insulating encapsulant, a protection layer and electrical connectors. The interconnection structure has a first surface and a second surface. The semiconductor die is disposed on the first surface and electrically connected to the interconnection structure. The insulating encapsulant is encapsulating the semiconductor die and partially covering sidewalls of the interconnection structure. The protection layer is disposed on the second surface of the interconnection structure and partially covering the sidewalls of the interconnection structure, wherein the protection layer is in contact with the insulating encapsulant. The electrical connectors are disposed on the protection layer, wherein the interconnection structure is electrically connected to the circuit substrate through the plurality of electrical connectors.
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公开(公告)号:US11150404B2
公开(公告)日:2021-10-19
申请号:US16542485
申请日:2019-08-16
发明人: Sung-Hui Huang , Jui Hsieh Lai , Tien-Yu Huang , Wen-Cheng Chen , Yushun Lin
摘要: A method includes bonding an electronic die to a photonic die. The photonic die includes an opening. The method further includes attaching an adapter onto the photonic die, with a portion of the adapter being at a same level as a portion of the electronic die, forming a through-hole penetrating through the adapter, with the through-hole being aligned to the opening, and attaching an optical device to the adapter. The optical device is configured to emit a light into the photonic die or receive a light from the photonic die.
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公开(公告)号:US10707177B2
公开(公告)日:2020-07-07
申请号:US16049015
申请日:2018-07-30
发明人: Sung-Hui Huang , Da-Cyuan Yu , Kuan-Yu Huang , Pai Yuan Li , Hsiang-Fan Lee
IPC分类号: H01L21/48 , H01L23/367 , H01L23/00 , H01L23/373 , H01L21/56 , H01L23/31 , H01L23/498 , H01L25/065 , H01L25/18 , H01L25/00
摘要: A package includes a package component, a device die over and bonded to the package component, a metal cap having a top portion over the device die, and a thermal interface material between and contacting the device die and the metal cap. The thermal interface material includes a first portion directly over an inner portion of the device die, and a second portion extending directly over a corner region of the device die. The first portion has a first thickness. The second portion has a second thickness greater than the first thickness.
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公开(公告)号:US20200006178A1
公开(公告)日:2020-01-02
申请号:US16569972
申请日:2019-09-13
发明人: Kuan-Yu Huang , Chih-Wei Wu , Li-Chung Kuo , Long Hua Lee , Sung-Hui Huang , Ying-Ching Shih , Pai Yuan Li
摘要: In order to prevent cracks from occurring at the corners of semiconductor dies after the semiconductor dies have been bonded to other substrates, an opening is formed adjacent to the corners of the semiconductor dies, and the openings are filled and overfilled with a buffer material that has physical properties that are between the physical properties of the semiconductor die and an underfill material that is placed adjacent to the buffer material.
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公开(公告)号:US10459159B2
公开(公告)日:2019-10-29
申请号:US16390565
申请日:2019-04-22
发明人: Sung-Hui Huang , Jui Hsieh Lai , Tien-Yu Huang , Wen-Cheng Chen , Yushun Lin
摘要: A method includes bonding an electronic die to a photonic die. The photonic die includes an opening. The method further includes attaching an adapter onto the photonic die, with a portion of the adapter being at a same level as a portion of the electronic die, forming a through-hole penetrating through the adapter, with the through-hole being aligned to the opening, and attaching an optical device to the adapter. The optical device is configured to emit a light into the photonic die or receive a light from the photonic die.
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公开(公告)号:US20190237454A1
公开(公告)日:2019-08-01
申请号:US16051848
申请日:2018-08-01
发明人: Shang-Yun Hou , Sung-Hui Huang , Kuan-Yu Huang , Hsien-Pin Hu , Yushun Lin , Heh-Chang Huang , Hsing-Kuo Hsia , Chih-Chieh Hung , Ying-Ching Shih , Chin-Fu Kao , Wen-Hsin Wei , Li-Chung Kuo , Chi-Hsi Wu , Chen-Hua Yu
IPC分类号: H01L25/00 , H01L25/065 , H01L23/24 , H01L23/31 , H01L23/498 , H01L21/48
CPC分类号: H01L25/50 , H01L21/4803 , H01L21/4853 , H01L23/24 , H01L23/3128 , H01L23/49827 , H01L24/16 , H01L25/0652 , H01L25/0655 , H01L2224/16235
摘要: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.
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