公开(公告)号：US11756870B2

公开(公告)日：2023-09-12

申请号：US17243600

申请日：2021-04-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Che-Yu Yeh ,  Tsung-Shu Lin ,  Wei-Cheng Wu ,  Tsung-Yu Chen ,  Li-Han Hsu ,  Chien-Fu Tseng

IPC分类号： H01L23/498 ,  H01L23/48 ,  H01L25/065 ,  H01L23/00

CPC分类号： H01L23/49822 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/20 ,  H01L24/24 ,  H01L25/0652 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/2105 ,  H01L2224/24226 ,  H01L2924/182

摘要： A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.

公开(公告)号：US20230369189A1

公开(公告)日：2023-11-16

申请号：US18357987

申请日：2023-07-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Che-Yu Yeh ,  Tsung-Shu Lin ,  Wei-Cheng Wu ,  Tsung-Yu Chen ,  Li-Han Hsu ,  Chien-Fu Tseng

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065

CPC分类号： H01L23/49822 ,  H01L24/20 ,  H01L23/49838 ,  H01L23/49816 ,  H01L23/481 ,  H01L24/24 ,  H01L25/0652 ,  H01L2224/214 ,  H01L2224/2105 ,  H01L2224/2101 ,  H01L2924/182 ,  H01L2224/24226

摘要： A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.

公开(公告)号：US20240178086A1

公开(公告)日：2024-05-30

申请号：US18169177

申请日：2023-02-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Che-Yu Yeh ,  Chien-Chia Chiu ,  Hua-Wei Tseng ,  Wan-Yu Lee

IPC分类号： H01L23/24 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/10 ,  H01L25/16

CPC分类号： H01L23/24 ,  H01L21/568 ,  H01L23/3121 ,  H01L24/24 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L24/48 ,  H01L2224/24101 ,  H01L2224/24155 ,  H01L2224/48228 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043

摘要： Disclosed are a package, a package structure and a method of manufacturing a package structure. In one embodiment, the package includes a die, a plurality of through vias, at least one dummy structure, an encapsulant and a redistribution structure. The plurality of through vias surround the die. The at least one dummy structure is disposed between the die and the plurality of through vias and adjacent to at least one corner of the die. The encapsulant encapsulates the die, the plurality of through vias and the at least one dummy structure. The redistribution structure is disposed on the die, the plurality of through vias, the at least one dummy structure and the encapsulant and electrically connected to the die and the plurality of through vias.

公开(公告)号：US20220352060A1

公开(公告)日：2022-11-03

申请号：US17243600

申请日：2021-04-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Che-Yu Yeh ,  Tsung-Shu Lin ,  Wei-Cheng Wu ,  Tsung-Yu Chen ,  Li-Han Hsu ,  Chien-Fu Tseng

IPC分类号： H01L23/498 ,  H01L23/48 ,  H01L25/065 ,  H01L23/00

摘要： A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.