公开(公告)号：US12094770B2

公开(公告)日：2024-09-17

申请号：US17446398

申请日：2021-08-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yao-Min Liu ,  Ming-Yuan Gao ,  Ming-Chou Chiang ,  Shu-Cheng Chin ,  Huei-Wen Hsieh ,  Kai-Shiang Kuo ,  Yen-Chun Lin ,  Cheng-Hui Weng ,  Chun-Chieh Lin ,  Hung-Wen Su

IPC分类号： H01L21/768 ,  H01L21/304 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76841 ,  H01L21/304 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238

摘要： In some implementations, one or more semiconductor processing tools may form a via within a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a ruthenium-based liner within the via. The one or more semiconductor processing tools may deposit, after depositing the ruthenium-based liner, a copper plug within the via.

公开(公告)号：US11508631B2

公开(公告)日：2022-11-22

申请号：US17017617

申请日：2020-09-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yen-Chun Lin ,  Bao-Ru Young ,  Ting-Yun Wu ,  Yen-Sen Wang ,  Hsiao-Wen Hsu

IPC分类号： H01L23/544 ,  H01L21/66

摘要： A semiconductor device may include function circuits and a test line structure beside the function circuits. The test line structure includes standard cell circuit blocks including a first components and environment circuit regions between the standard cell circuit blocks. The environment circuit regions include second components. The first components are different from the second components in structure, arrangement or a combination thereof.

公开(公告)号：US09768277B2

公开(公告)日：2017-09-19

申请号：US14815375

申请日：2015-07-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Lung Cheng ,  Da-Wen Lin ,  Yen-Chun Lin

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/165

CPC分类号： H01L29/66795 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/511 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7847 ,  H01L29/7848

摘要： Various methods include providing a substrate, forming a projection extending upwardly from the substrate, the projection having a channel region therein, and forming a gate structure engaging the projection adjacent to the channel region, the gate structure having spaced first and second conductive layers and a strain-inducing conductive layer disposed between the first and second conductive layers. The method also includes forming epitaxial growths on portions of the projection at each side of the gate structure, the epitaxial growths imparting a first strain to the channel region, and imparting a second strain to the channel region, including performing at least one stress memorization technique on the gate structure such that the strain-inducing conductive layer imparts the second strain to the channel region, and removing the capping layer, wherein the imparting the second strain is carried out in a manner that imparts tensile strain to the channel region.

公开(公告)号：US20190103487A1

公开(公告)日：2019-04-04

申请号：US16122793

申请日：2018-09-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Ling Chan ,  Yen-Chun Lin

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L23/532 ,  H01L29/423 ,  H01L21/768 ,  H01L21/308 ,  H01L21/8238 ,  H01L21/324 ,  H01L21/22

摘要： A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, forming a first spacer over the dummy gate structure, implanting a first dopant in the fin to form a doped region of the fin adjacent the first spacer, removing the doped region of the fin to form a first recess, wherein the first recess is self-aligned to the doped region, and epitaxially growing a source/drain region in the first recess.

公开(公告)号：US09412870B2

公开(公告)日：2016-08-09

申请号：US14833268

申请日：2015-08-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： King-Yuen Wong ,  Chia-Yu Lu ,  Chien-Chang Su ,  Yen-Chun Lin ,  Yi-Fang Pai ,  Da-Wen Lin

IPC分类号： H01L21/02 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8249 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L27/06 ,  H01L29/04 ,  H01L29/167

CPC分类号： H01L29/0847 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/045 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A device includes a substrate and a recess in the substrate. The recess has a bottom and sidewalls. The device also includes a first epitaxial layer over the bottom of the recess, and a second epitaxial layer over the first epitaxial layer and over the sidewalls of the recess, the second epitaxial layer having a different lattice constant than the substrate. The device further includes a third epitaxial layer over the second epitaxial layer and filling the recess.

摘要翻译： 一种器件包括衬底和衬底中的凹部。 凹槽具有底部和侧壁。 该器件还包括在凹槽的底部上的第一外延层，以及位于第一外延层上方的第二外延层，并且在凹槽的侧壁之上，第二外延层具有与衬底不同的晶格常数。 该器件还包括在第二外延层上方的第三外延层并填充凹陷。

公开(公告)号：US20150364602A1

公开(公告)日：2015-12-17

申请号：US14833268

申请日：2015-08-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： King-Yuen Wong ,  Chia-Yu Lu ,  Chien-Chang Su ,  Yen-Chun Lin ,  Yi-Fang Pai ,  Da-Wen Lin

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L21/02 ,  H01L29/167 ,  H01L29/04 ,  H01L27/06 ,  H01L29/66 ,  H01L29/165

CPC分类号： H01L29/0847 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/045 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A device includes a substrate and a recess in the substrate. The recess has a bottom and sidewalls. The device also includes a first epitaxial layer over the bottom of the recess, and a second epitaxial layer over the first epitaxial layer and over the sidewalls of the recess, the second epitaxial layer having a different lattice constant than the substrate. The device further includes a third epitaxial layer over the second epitaxial layer and filling the recess.

摘要翻译： 一种器件包括衬底和衬底中的凹部。 凹槽具有底部和侧壁。 该器件还包括在凹槽的底部上的第一外延层，以及位于第一外延层上方的第二外延层，并且在凹槽的侧壁之上，第二外延层具有与衬底不同的晶格常数。 该器件还包括在第二外延层上方的第三外延层并填充凹陷。

公开(公告)号：US20150340293A1

公开(公告)日：2015-11-26

申请号：US14815375

申请日：2015-07-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Lung Cheng ,  Da-Wen Lin ,  Yen-Chun Lin

IPC分类号： H01L21/8238 ,  H01L21/324 ,  H01L29/51 ,  H01L21/02 ,  H01L29/165 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/511 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7847 ,  H01L29/7848

摘要： Various methods include providing a substrate, forming a projection extending upwardly from the substrate, the projection having a channel region therein, and forming a gate structure engaging the projection adjacent to the channel region, the gate structure having spaced first and second conductive layers and a strain-inducing conductive layer disposed between the first and second conductive layers. The method also includes forming epitaxial growths on portions of the projection at each side of the gate structure, the epitaxial growths imparting a first strain to the channel region, and imparting a second strain to the channel region, including performing at least one stress memorization technique on the gate structure such that the strain-inducing conductive layer imparts the second strain to the channel region, and removing the capping layer, wherein the imparting the second strain is carried out in a manner that imparts tensile strain to the channel region.

摘要翻译： 各种方法包括提供基板，形成从基板向上延伸的突起，突起在其中具有通道区域，以及形成接合邻近通道区域的突起的栅极结构，栅极结构具有间隔开的第一和第二导电层以及 应变诱发导电层设置在第一和第二导电层之间。 所述方法还包括在所述栅极结构的每一侧的所述突起的部分上形成外延生长，所述外延生长对所述沟道区赋予第一应变，并且向所述沟道区赋予第二应变，包括执行至少一个应力记忆技术 在栅极结构上使得应变诱导导电层将第二应变施加到沟道区，并且去除覆盖层，其中赋予第二应变以赋予沟道区的拉伸应变的方式进行。

公开(公告)号：US11688654B2

公开(公告)日：2023-06-27

申请号：US17331675

申请日：2021-05-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yen-Chun Lin ,  Chung-Yi Lin ,  Yen-Sen Wang ,  Bao-Ru Young

IPC分类号： H01L21/66 ,  H01L23/528 ,  H01L23/00 ,  G06F30/3947

CPC分类号： H01L22/32 ,  G06F30/3947 ,  H01L22/14 ,  H01L23/528 ,  H01L24/05

摘要： Test line structures are provided. A test line structure includes a semiconductor substrate, a plurality of diagnosis units and a plurality of first micro pad units. The diagnosis units are formed over the semiconductor substrate. Each of the diagnosis units includes a first interconnect structure having a first routing pattern. The first interconnect structures of the diagnosis units are connected in series to form a first test chain through the first micro pad units, and each of the first micro pad units is configured to connect the first interconnect structures of two adjacent diagnosis units in the first test chain. The first routing patterns of the first interconnect structures in the diagnosis units are different.

公开(公告)号：US20180374760A1

公开(公告)日：2018-12-27

申请号：US15633418

申请日：2017-06-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Ling Chan ,  Yen-Chun Lin

IPC分类号： H01L21/8238 ,  H01L21/3115 ,  H01L21/324 ,  H01L21/223 ,  H01L29/08 ,  H01L29/66 ,  H01L21/266 ,  H01L21/225

摘要： A method includes forming a spacer layer over a semiconductor fin protruding above a substrate, doping the spacer layer using a first dopant while the spacer layer covers source/drain regions of the semiconductor fin, and performing a thermal anneal process after the doping.

公开(公告)号：US20210125883A1

公开(公告)日：2021-04-29

申请号：US17017617

申请日：2020-09-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yen-Chun Lin ,  Bao-Ru Young ,  Ting-Yun Wu ,  Yen-Sen Wang ,  Hsiao-Wen Hsu

IPC分类号： H01L21/66 ,  H01L23/544

摘要： A semiconductor device may include function circuits and a test line structure beside the function circuits. The test line structure includes standard cell circuit blocks including a first components and environment circuit regions between the standard cell circuit blocks. The environment circuit regions include second components. The first components are different from the second components in structure, arrangement or a combination thereof.