公开(公告)号：US11923425B2

公开(公告)日：2024-03-05

申请号：US18170709

申请日：2023-02-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Cheng Chiu ,  Tian Sheng Lin ,  Hung-Chou Lin ,  Yi-Min Chen ,  Chiu-Hua Chung

IPC分类号： H01L29/40 ,  H01L21/765 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/402 ,  H01L21/765 ,  H01L29/0653 ,  H01L29/66681 ,  H01L29/7816

摘要： A method for manufacturing a device may include providing an ultra-high voltage (UHV) component that includes a source region and a drain region, and forming an oxide layer on a top surface of the UHV component. The method may include connecting a low voltage terminal to the source region of the UHV component, and connecting a high voltage terminal to the drain region of the UHV component. The method may include forming a shielding structure on a surface of the oxide layer provided above the drain region of the UHV component, forming a high voltage interconnection that connects to the shielding structure and to the high voltage terminal, and forming a metal routing that connects the shielding structure and the low voltage terminal.

公开(公告)号：US20210399087A1

公开(公告)日：2021-12-23

申请号：US17462403

申请日：2021-08-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Karthick Murukesan ,  Wen-Chih Chiang ,  Chun Lin Tsai ,  Ker-Hsiao Huo ,  Kuo-Ming Wu ,  Po-Chih Chen ,  Ru-Yi Su ,  Shiuan-Jeng Lin ,  Yi-Min Chen ,  Hung-Chou Lin ,  Yi-Cheng Chiu

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/10 ,  H03K19/0185 ,  H01L27/088

摘要： Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.

公开(公告)号：US12062687B2

公开(公告)日：2024-08-13

申请号：US18215707

申请日：2023-06-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hong-Yang Chen ,  Tian Sheng Lin ,  Yi-Cheng Chiu ,  Hung-Chou Lin ,  Yi-Min Chen ,  Kuo-Ming Wu ,  Chiu-Hua Chung

IPC分类号： H01L27/108 ,  H01L27/01 ,  H01L27/06 ,  H01L29/76 ,  H01L31/119 ,  H01L49/02

CPC分类号： H01L28/60 ,  H01L27/01 ,  H01L27/0629

摘要： A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.

公开(公告)号：US11728374B2

公开(公告)日：2023-08-15

申请号：US17498561

申请日：2021-10-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hong-Yang Chen ,  Tian Sheng Lin ,  Yi-Cheng Chiu ,  Hung-Chou Lin ,  Yi-Min Chen ,  Kuo-Ming Wu ,  Chiu-Hua Chung

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L31/119 ,  H01L49/02 ,  H01L27/01 ,  H01L27/06

CPC分类号： H01L28/60 ,  H01L27/01 ,  H01L27/0629

摘要： A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.

公开(公告)号：US20160260704A1

公开(公告)日：2016-09-08

申请号：US14638407

申请日：2015-03-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ker-Hsiao Huo ,  Hsin-Chih Chiang ,  Kevin Chen ,  Chun Lin Tsai ,  Yi-Min Chen

IPC分类号： H01L27/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L21/768 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/762 ,  H01L49/02 ,  H01L29/06

CPC分类号： H01L27/0629 ,  H01L21/76202 ,  H01L28/20 ,  H01L29/063 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/405 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816

摘要： A high voltage semiconductor device includes: a source having a first conductivity type and a drain having the first conductivity type disposed in a substrate; a first dielectric component disposed on a surface of the substrate between the source and the drain; a drift region disposed in the substrate, wherein the drift region has the first conductivity type; a first doped region having a second conductivity type and disposed within the drift region under the dielectric component, the second conductivity type being opposite the first conductivity type; a second doped region having the second conductivity type and disposed within the drift region, wherein the second doped region at least partially surrounds one of the source and the drain; a resistor disposed directly on the dielectric component; and a gate disposed directly on the dielectric component, wherein the gate is electrically coupled to the resistor.

摘要翻译： 高电压半导体器件包括：具有第一导电类型的源极和具有设置在衬底中的第一导电类型的漏极; 设置在源极和漏极之间的衬底的表面上的第一介电部件; 设置在所述衬底中的漂移区，其中所述漂移区具有第一导电类型; 第一掺杂区域，具有第二导电类型并且设置在介电部件下方的漂移区域内，第二导电类型与第一导电类型相反; 具有第二导电类型并且设置在漂移区内的第二掺杂区，其中第二掺杂区至少部分地围绕源极和漏极之一; 直接设置在电介质部件上的电阻器; 以及直接设置在所述电介质部件上的栅极，其中所述栅极电耦合到所述电阻器。

公开(公告)号：US20220336659A1

公开(公告)日：2022-10-20

申请号：US17852802

申请日：2022-06-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hung-Chou Lin ,  Yi-Cheng Chiu ,  Karthick Murukesan ,  Yi-Min Chen ,  Shiuan-Jeng Lin ,  Wen-Chih Chiang ,  Chen-Chien Chang ,  Chih-Yuan Chan ,  Kuo-Ming Wu ,  Chun-Lin Tsai

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/40 ,  H01L29/06 ,  H01L29/423

摘要： A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.

公开(公告)号：US20240332065A1

公开(公告)日：2024-10-03

申请号：US18191290

申请日：2023-03-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yao-Hong You ,  Dah-Chuen Ho ,  Kuo-Ming Wu ,  Ying-De Chen ,  Yi-Min Chen

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53219 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53257

摘要： The present disclosure relates to a method of forming an interconnect structure that eliminates a separate deep via patterning process to simplify the fabrication process. In some embodiments, a first dielectric layer is formed over a first metal line and patterned to form a through-hole exposing a first contact region of the first metal line. A second dielectric layer is deposited and patterned to form a first via-hole connecting to the through-hole and a second via-hole exposing a second contact region of the second metal line from a layout view. A first via is formed on the first contact region extending to a first upper surface of the second dielectric layer, and a second via is formed on the second contact region extending to a second upper surface of the second dielectric layer.

公开(公告)号：US20230343816A1

公开(公告)日：2023-10-26

申请号：US18215707

申请日：2023-06-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hong-Yang CHEN ,  Tian Sheng Lin ,  Yi-Cheng Chiu ,  Hung-Chou Lin ,  Yi-Min Chen ,  Kuo-Ming Wu ,  Chiu-Hua Chung

IPC分类号： H01G4/30 ,  H01L27/01 ,  H01L27/06

CPC分类号： H01L28/60 ,  H01L27/01 ,  H01L27/0629

摘要： A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.

公开(公告)号：US10930776B2

公开(公告)日：2021-02-23

申请号：US15929547

申请日：2020-05-08

申请人： Taiwan Semiconductor Manufacturing Company Ltd.

发明人： Ker-Hsiao Huo ,  Kong-Beng Thei ,  Chien-Chih Chou ,  Yi-Min Chen ,  Chen-Liang Chu

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

摘要： A semiconductor device is provided. The semiconductor device comprises a substrate, a gate, a first doped region and a second doped region. The gate is over the substrate. The first doped region and the second doped region are in the substrate. The first doped region and the second doped region are of a same conductivity type and separated by the gate. The length of the first doped region is greater than a length of the second doped region in a direction substantially perpendicular to a channel length defined between the first doped region and the second doped region.

公开(公告)号：US10790387B2

公开(公告)日：2020-09-29

申请号：US15912191

申请日：2018-03-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ker-Hsiao Huo ,  Kong-Beng Thei ,  Chien-Chih Chou ,  Yi-Min Chen ,  Chen-Liang Chu

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

摘要： A semiconductor device is provided. The semiconductor device comprises a substrate, a gate, a first doped region and a second doped region. The gate is over the substrate. The first doped region and the second doped region are in the substrate. The first doped region and the second doped region are of a same conductivity type and separated by the gate. The length of the first doped region is greater than a length of the second doped region in a direction substantially perpendicular to a channel length defined between the first doped region and the second doped region.