公开(公告)号：US20240250133A1

公开(公告)日：2024-07-25

申请号：US18099146

申请日：2023-01-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wu-Wei TSAI ,  Chi-Min CHEN ,  Yin-Hao WU ,  Kai-Wen CHENG ,  Hai-Ching CHEN ,  Yu-Ming LIN ,  Chung-Te LIN

IPC分类号： H01L29/417 ,  H01L29/40 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L29/41733 ,  H01L29/401 ,  H01L29/66969 ,  H01L29/7869

摘要： A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate electrode, a gate insulating layer, an active layer, a dielectric layer, a source electrode, and a drain electrode. The gate insulating layer is disposed between the gate electrode and the active layer, the dielectric layer is disposed on a side of the active layer, and the source electrode and the drain electrode pass through the dielectric layer to electrically connect with the active layer, wherein a first contact surface is formed between the source electrode and the active layer, a second contact surface is formed between the drain electrode and the active layer, the first contact surface and the second contact surface are subjected to a plasma treatment or a deposition treatment to form a protective interface layer.

公开(公告)号：US20240162094A1

公开(公告)日：2024-05-16

申请号：US18405040

申请日：2024-01-05

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shih-Chuan CHIU ,  Jia-Chuan YOU ,  Chia-Hao CHANG ,  Chun-Yuan CHEN ,  Tien-Lu LIN ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC分类号： H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823475 ,  H01L21/76829 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/5226 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a conductive feature on the substrate, and an electrical connection structure on the conductive feature. The electrical connection includes a first grain made of a first metal material, and a first inhibition layer made of a second metal layer that is different than the first metal material. The first inhibition layer extends vertically along a first side of a grain boundary of the first grain and laterally along a bottom of the grain boundary of the first grain.

公开(公告)号：US20240071504A1

公开(公告)日：2024-02-29

申请号：US17898733

申请日：2022-08-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Pei-Chun LIAO ,  Yu-Kai CHANG ,  Yi-Ching LIU ,  Yu-Ming LIN ,  Yih WANG ,  Chieh LEE

IPC分类号： G11C16/08 ,  G11C16/26 ,  G11C16/32

CPC分类号： G11C16/08 ,  G11C16/26 ,  G11C16/32

摘要： A memory device is provided, including a memory array, a driver circuit, and recover circuit. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.

公开(公告)号：US20230207383A1

公开(公告)日：2023-06-29

申请号：US18053016

申请日：2022-11-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Yuan CHEN ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC分类号： H01L21/76816 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53209

摘要： A method for forming a semiconductor device structure is provided. The method includes forming a first conductive structure surrounded by a first dielectric layer and forming a second dielectric layer over the first conductive structure and the first dielectric layer. The method also includes forming a via hole in the second dielectric layer, and the via hole exposes the first conductive structure. The method further includes partially removing the first conductive structure through the via hole to form a recess in the first conductive structure. In addition, the method includes forming a second conductive structure filling the recess and the via hole.

公开(公告)号：US20230197145A1

公开(公告)日：2023-06-22

申请号：US17554183

申请日：2021-12-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Huai-Ying HUANG ,  Yu-Ming LIN

IPC分类号： G11C11/413

CPC分类号： G11C11/413

摘要： A device is disclosed, including a latch circuit, a first pass-gate transistor, and a second pass-gate transistor. The latch circuit stores a bit data and is arranged in a first layer. The first pass-gate transistor and the second pass-gate transistor are arranged in a second layer separated from the first layer. The first pass-gate transistor is coupled between a first bit line and a first terminal of the latch circuit, and the second pass-gate transistor is coupled between a second bit line and a second terminal of the latch circuit.

公开(公告)号：US20220406798A1

公开(公告)日：2022-12-22

申请号：US17721814

申请日：2022-04-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chao-I WU ,  Yu-Ming LIN

IPC分类号： H01L27/1159 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66

摘要： Some embodiments of a method for manufacturing integrated circuits include the operations of forming a back gate structure on a substrate, forming a memory layer over the back gate structure, forming a buffer layer over the memory layer, forming a conductive channel over the buffer layer, and forming source/drain regions over the conductive channel. In some embodiments, a second buffer layer is formed between the back gate structure and the memory layer.

公开(公告)号：US20210098307A1

公开(公告)日：2021-04-01

申请号：US17120689

申请日：2020-12-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Lin-Yu HUANG ,  Sheng-Tsung WANG ,  Jia-Chuan YOU ,  Chia-Hao CHANG ,  Tien-Lu LIN ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC分类号： H01L21/8234 ,  H01L29/40 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/08

摘要： Semiconductor device structures are provided. The semiconductor device structure includes a substrate and a first fin structure protruding from the substrate. The semiconductor device structure further includes a gate stack formed across the first fin structure and a first source/drain structure formed over the first fin structure adjacent to the gate stack. The semiconductor device structure further includes a contact structure formed over the first source/drain structure and a dielectric structure formed through the contact structure. In addition, a bottom surface of the contact structure is wider than a top surface of the contact structure.

公开(公告)号：US20240234582A1

公开(公告)日：2024-07-11

申请号：US18151141

申请日：2023-01-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wu-Wei TSAI ,  Hai-Ching CHEN ,  Kai-Wen CHENG ,  Yu-Ming LIN ,  Chung-Te LIN

IPC分类号： H01L29/786 ,  H01L21/8234 ,  H01L29/417

CPC分类号： H01L29/78696 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/41733 ,  H01L29/7869

摘要： A semiconductor device includes a gate electrode, a gate dielectric located over the gate electrode, a channel layer including a semiconductor material and located over the gate dielectric, blocking layers located over the channel layer, covering portions of channel layer, and spaced apart from each other, buffer layers respectively located over the blocking layers, respectively surrounded by the blocking layers, and including a material that receives hydrogen, and source/drain contacts respectively located over the buffer layers and respectively surrounded by the buffer layers.

公开(公告)号：US20220384264A1

公开(公告)日：2022-12-01

申请号：US17818443

申请日：2022-08-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Lin-Yu HUANG ,  Sheng-Tsung WANG ,  Jia-Chuan YOU ,  Chia-Hao CHANG ,  Tien-Lu LIN ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC分类号： H01L21/8234 ,  H01L29/40 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/08 ,  H01L29/417

摘要： Semiconductor device structures are provided. The semiconductor device structure includes a substrate and a first fin structure protruding from the substrate. The semiconductor device structure further includes an isolation layer formed around the first fin structure and covering a sidewall of the first fin structure and a gate stack formed over the first fin structure and the isolation layer. The semiconductor device structure further includes a first source/drain structure formed over the first fin structure and spaced apart from the gate stack and a contact structure formed over the first source/drain structure. The semiconductor device structure includes a dielectric structure formed through the contact structure. In addition, the contact structure and the dielectric structure has a first slope interface that slopes downwardly from a top surface of the contact structure to a top surface of the isolation layer.

公开(公告)号：US20220352183A1

公开(公告)日：2022-11-03

申请号：US17243732

申请日：2021-04-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chenchen Jacob WANG ,  Sai-Hooi YEONG ,  Bo-Feng YOUNG ,  Chun-Chieh LU ,  Yu-Ming LIN

IPC分类号： H01L27/1159 ,  H01L27/11587 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

摘要： A semiconductor memory structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes spacers formed over opposite sides of the gate structure. The structure also includes source/drain epitaxial structures formed on opposite sides of the gate structure beside the spacers. The gate structure includes a III-V ferroelectric layer formed between an interfacial layer and a gate electrode layer.