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公开(公告)号：US20050185483A1
公开(公告)日：2005-08-25
申请号：US11061365
申请日：2005-02-18
申请人： Akira Sugiura , Takaaki Furuyama
发明人： Akira Sugiura , Takaaki Furuyama
CPC分类号： G11C29/82 , G11C29/70 , G11C29/808
摘要： A semiconductor memory device includes a memory block having memory cells connected to global bit lines and global word lines are arranged in matrix constitutes a memory block column sharing global bit lines, the memory block column being developed in global word line wiring direction, wherein at least two of memory block columns adjoining each other constitute a to-be-remedied unit, and redundant block(s), which is/are arranged sharing global bit lines with the memory block column(s), which is/are provided in each to-be-remedied unit and number of redundant block(s) is/are smaller than that of memory block column(s) included in the to-be-remedied unit. A minimum number of redundant memory blocks necessary for defectiveness remedy can be provided thereby enhancing the yield with optimization of the manufacturing and circuits. Redundancy remedy efficiency can also be improved while minimizing increased chip die size of the semiconductor memory device.
摘要翻译： 半导体存储器件包括具有连接到全局位线的存储器单元的存储器块，并且矩阵排列的全局字线构成共享全局位线的存储器块列，所述存储器块列在全局字线布线方向上显影，其中至少 彼此相邻的两个存储器块列构成待修复的单元，并且被配置为与存储器块列共享全局位线的冗余块，每一个被提供在每个到 补救单元和冗余块的数量小于待修复单元中包含的存储块列的数量。 可以提供缺陷补救所需的最少数量的冗余存储块，从而通过优化制造和电路来提高产量。 还可以提高冗余补救效率，同时最小化半导体存储器件的芯片尺寸增加。
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公开(公告)号：US07061816B2
公开(公告)日：2006-06-13
申请号：US11061365
申请日：2005-02-18
申请人： Akira Sugiura , Takaaki Furuyama
发明人： Akira Sugiura , Takaaki Furuyama
IPC分类号： G11C7/00
CPC分类号： G11C29/82 , G11C29/70 , G11C29/808
摘要： A semiconductor memory device includes a memory block having memory cells connected to global bit lines and global word lines are arranged in matrix constitutes a memory block column sharing global bit lines, the memory block column being developed in global word line wiring direction, wherein at least two of memory block columns adjoining each other constitute a to-be-remedied unit, and redundant block(s), which is/are arranged sharing global bit lines with the memory block column(s), which is/are provided in each to-be-remedied unit and number of redundant block(s) is/are smaller than that of memory block column(s) included in the to-be-remedied unit. A minimum number of redundant memory blocks necessary for defectiveness remedy can be provided thereby enhancing the yield with optimization of the manufacturing and circuits. Redundancy remedy efficiency can also be improved while minimizing increased chip die size of the semiconductor memory device.
摘要翻译： 半导体存储器件包括具有连接到全局位线的存储器单元的存储器块，并且矩阵排列的全局字线构成共享全局位线的存储器块列，所述存储器块列在全局字线布线方向上显影，其中至少 彼此相邻的两个存储器块列构成待修复的单元，并且被配置为与存储器块列共享全局位线的冗余块，每一个被提供在每个到 补救单元和冗余块的数量小于待修复单元中包含的存储块列的数量。 可以提供缺陷补救所需的最少数量的冗余存储块，从而通过优化制造和电路来提高产量。 还可以提高冗余补救效率，同时最小化半导体存储器件的芯片尺寸增加。
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公开(公告)号：US5787046A
公开(公告)日：1998-07-28
申请号：US636801
申请日：1996-04-23
申请人： Takaaki Furuyama , Akira Sugiura
发明人： Takaaki Furuyama , Akira Sugiura
IPC分类号： G11C11/401 , G11C7/10 , G11C11/407 , G11C13/00
CPC分类号： G11C7/10 , G11C7/1015
摘要： A semiconductor memory device is operable in an operation mode selected from a read mode, a normal write mode and a block write mode. The memory device includes a memory cell array having a plurality of pairs of bit lines, a plurality of word lines and a plurality of memory cells provided at intersections of the bit lines and the word lines, wherein each pair of the bit lines and the memory cells associated with each bit line pair form one of a plurality of columns defined in the memory cell array. The memory device also includes a pair of data lines and a column selection controller, wherein the column selection controller is supplied with a group of column selection signals for selectively connecting and disconnecting the pair of data lines to and from the plurality of pairs of bit lines. In response to the group of column selection signals with a first signal output pattern for use in the normal write mode or the read mode, the column selection controller selects one of the plurality of columns to connect the pair of data lines to a pair of bit lines associated with the select column. Further, in response to the group of column selection signals with a second signal output pattern for use in the block write mode, the column selection controller selects at least two of the plurality of columns to connect the pair of data lines to the bit line pairs associated with a column block as a group of the selected columns.
摘要翻译： 半导体存储器件可以在从读取模式，正常写入模式和块写入模式中选择的操作模式中操作。 存储器件包括存储单元阵列，其具有多个位线对，多个字线和设置在位线和字线的交点处的多个存储单元，其中每对位线和存储器 与每个位线对相关联的单元形成在存储单元阵列中定义的多个列之一。 存储装置还包括一对数据线和列选择控制器，其中列选择控制器被提供有一组列选择信号，用于选择性地连接和断开与多对位线对之间的数据线对 。 响应于具有用于正常写入模式或读取模式的第一信号输出模式的列选择信号组，列选择控制器选择多个列之一将数据线对连接到一对位 与选择列关联的行。 此外，响应于具有用于块写入模式的第二信号输出模式的列选择信号组，列选择控制器选择多个列中的至少两个将数据线对连接到位线对 与列块相关联，作为所选列的组。
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公开(公告)号：US4818458A
公开(公告)日：1989-04-04
申请号：US926625
申请日：1986-11-04
申请人： Akira Sugiura , Shigeru Sawanishi , Noboru Ogawa
发明人： Akira Sugiura , Shigeru Sawanishi , Noboru Ogawa
摘要： A spinning solution of an acrylonitrile polymer is subjected to dry-wet spinning through an annular type spinneret having a non-perforated part, i.e. a part not formed with spinning orifices, extending from the outer periphery to the inner periphery. The spinneret has more than 3,000 spinning orifices, at the perforated part of the annular portion. The extruded fibers are then passed through a coagulation bath, and the coagulated fibers are then stretched. By this method, uniform acrylic fibers can be produced without causing quality unevenness and fiber defects due to uneven coagulation, filament agglutination, and fluctuation of the gap between spinneret lower surface and liquid surface of the coagulation bath.
摘要翻译： 将丙烯腈聚合物的纺丝溶液通过具有非穿孔部分的环形喷丝头进行干湿纺丝，即从外周向内周延伸的不具有纺丝孔的部分。 喷丝头在环形部分的穿孔部分有3000多个纺丝孔。 然后将挤出的纤维通过凝固浴，然后将凝固的纤维拉伸。 通过这种方法，可以产生均匀的丙烯酸纤维，而不会由于凝固不均匀，纤维凝集以及喷丝头下表面和凝固浴液面之间的间隙的波动而引起质量不均匀和纤维缺陷。
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公开(公告)号：US07621242B2
公开(公告)日：2009-11-24
申请号：US11637160
申请日：2006-12-12
IPC分类号： F01L1/34
CPC分类号： F01L13/0021 , F01L13/0063 , F01L2013/0068 , F01L2013/0073 , F01L2800/06 , F02D13/0203 , Y02T10/18
摘要： The present invention provides a variable valve operating mechanism which includes two valve operating members for opening and closing two valves individually, a drive cam provided on a single camshaft, two swing arms for transmitting a power of the drive cam to the valve operating members individually by swinging about a different axis to the camshaft, and a variable device for modifying a displacement of the swing arm per rotation of the drive cam in accordance with an operating condition of an internal combustion engine. The variable device includes a single control shaft, an actuator for driving the control shaft, and a cam device that operates in conjunction with the control shaft to dissimilate the displacement of the two swing arms.
摘要翻译： 本发明提供一种可变气门操作机构，其包括用于单独打开和关闭两个阀的两个气门操作构件，设置在单个凸轮轴上的驱动凸轮，两个摆动臂，用于将驱动凸轮的动力单独地传递到阀操作构件 围绕与凸轮轴不同的轴线摆动，以及可变装置，用于根据内燃机的运行状态改变每转动驱动凸轮的摆臂的位移。 可变装置包括单个控制轴，用于驱动控制轴的致动器以及与控制轴一起操作的凸轮装置，以消除两个摆臂的位移。
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公开(公告)号：US06885212B2
公开(公告)日：2005-04-26
申请号：US10356489
申请日：2003-02-03
申请人： Seiji Yamamoto , Hirosuke Koumyoji , Tohru Yasuda , Mikio Ishikawa , Isaya Sobue , Hajime Sato , Chiaki Furukawa , Akira Sugiura , Akihiro Iwase
发明人： Seiji Yamamoto , Hirosuke Koumyoji , Tohru Yasuda , Mikio Ishikawa , Isaya Sobue , Hajime Sato , Chiaki Furukawa , Akira Sugiura , Akihiro Iwase
CPC分类号： G01R31/04 , H01L2924/0002 , H01L2924/00
摘要： A multi-bus semiconductor device and a method of its probing test perform the DC test for individual pads of a device while dealing with an adequate number of devices for simultaneous measurement based on the scheme of input/output pad number compressive test. The semiconductor device includes switch elements SW0-SW4 connected between input/output pads P0-P4 and a testing line L0 so that pads in an arbitrary combination, among the off-probe pads P1-P4 that are not made in contact with the tester probe Pr0, are selected for testing in correspondence to the combination of switch elements that are turned on. The input/output buffers of the pads under test are deactivated to block their internal current paths. The corresponding switch elements are turned on to connect the off-probe pads under test to the probe pad P0 that is made in contact with the tester probe Pr0, and the leak current of the probes is measured with the tester TS.
摘要翻译： 多总线半导体器件及其探测测试方法基于输入/输出焊盘数压缩测试的方案，处理设备的各个焊盘的DC测试，同时处理足够数量的用于同时测量的设备。 半导体器件包括连接在输入/输出焊盘P 0 -P 4和测试线L 0之间的开关元件SW 0 -SW 4，使得不是非探针焊盘P 1 -P 4中的任意组合的焊盘 与测试仪探头Pr 0接触的选择被选择用于与打开的开关元件的组合相对应的测试。 被测试焊盘的输入/输出缓冲器被禁用以阻止其内部电流路径。 将相应的开关元件接通，将被测试的探针焊盘连接到与测试仪探头Pr 0接触的探针焊盘P 0，并用测试仪TS测量探头的漏电流。
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公开(公告)号：US5319607A
公开(公告)日：1994-06-07
申请号：US793970
申请日：1991-11-18
CPC分类号： G11C8/18
摘要： The present invention relates to a semiconductor unit including a delay circuit used for an address transition detecting circuit in a storage, wherein a change of an address is detected and, accordingly, an access address in a memory cell is altered. The present invention aims at ensuring extending an address signal even though that of a short pulse width is provided, and at outputting an address transition detection signal of a predetermined pulse width, thereby stabilizing the operation of the circuit and improving its reliability. The present invention includes a second address extending circuit having a complementary transistor circuit, a capacitor connected to the output part of the complementary transistor circuit, and a resistor serially connected between a pair of complementary transistors. A signal generating circuit for outputs an address transition detection signal in response to a non-inverted address signal, an inverted address signal, and output of the first and the second address extending circuits.
摘要翻译： 本发明涉及包括用于存储器中的地址转换检测电路的延迟电路的半导体单元，其中检测到地址的变化，因此改变了存储单元中的存取地址。 本发明的目的在于确保扩展地址信号，即使提供短脉冲宽度，并且输出预定脉冲宽度的地址转换检测信号，从而稳定电路的操作并提高其可靠性。 本发明包括具有互补晶体管电路的第二地址扩展电路，连接到互补晶体管电路的输出部分的电容器和串联连接在一对互补晶体管之间的电阻器。 一种信号发生电路，用于响应于非反相地址信号，反相地址信号和第一和第二地址扩展电路的输出输出地址转变检测信号。
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公开(公告)号：US07451729B2
公开(公告)日：2008-11-18
申请号：US11716745
申请日：2007-03-12
申请人： Akira Sugiura , Tetsuya Niwa , Tamotsu Yamamoto , Katsutoshi Kitagawa , Tomiyasu Hirano , Tomoki Miyoshi
发明人： Akira Sugiura , Tetsuya Niwa , Tamotsu Yamamoto , Katsutoshi Kitagawa , Tomiyasu Hirano , Tomoki Miyoshi
IPC分类号： F01L1/34
CPC分类号： F01L13/0021 , F01L2105/00 , F01L2820/032
摘要： The present invention provides a variable valve mechanism which includes a rotating cam provided on a camshaft, a swing arm that contacts with the rotating cam to swing, a drive arm that drives a valve in conjunction with the swing arm, a variable arm that turns the drive arm around a swing axis of the swing arm, an actuator that drives the variable arm, and cam device that is provided between the swing arm and the drive arm. The variable arm is provided so as to be able to rotate relatively around the same axis as the swing arm, and the cam device changes the initial position of the drive arm with respect to the swing arm accompanying the turning of the drive arm.
摘要翻译： 本发明提供一种可变阀机构，其包括设置在凸轮轴上的旋转凸轮，与旋转凸轮相接触的摆臂摆动，与摇臂结合驱动阀的驱动臂，使臂 围绕摆臂的摆动轴的驱动臂，驱动可变臂的致动器以及设置在摆臂和驱动臂之间的凸轮装置。 可变臂被设置成能够相对于与摆臂相同的轴线旋转，并且凸轮装置随着驱动臂的转动而改变驱动臂相对于摆臂的初始位置。
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公开(公告)号：US07330043B2
公开(公告)日：2008-02-12
申请号：US11079142
申请日：2005-03-15
申请人： Seiji Yamamoto , Hirosuke Koumyoji , Tohru Yasuda , Mikio Ishikawa , Isaya Sobue , Hajime Sato , Chiaki Furukawa , Akira Sugiura , Akihiro Iwase
发明人： Seiji Yamamoto , Hirosuke Koumyoji , Tohru Yasuda , Mikio Ishikawa , Isaya Sobue , Hajime Sato , Chiaki Furukawa , Akira Sugiura , Akihiro Iwase
CPC分类号： G01R31/04 , H01L2924/0002 , H01L2924/00
摘要： A multi-bus semiconductor device and a method of its probing test perform the DC test for individual pads of a device while dealing with an adequate number of devices for simultaneous measurement based on the scheme of input/output pad number compressive test. The semiconductor device includes switch elements SW0-SW4 connected between input/output pads P0-P4 and a testing line L0 so that pads in an arbitrary combination, among the off-probe pads P1-P4 that are not made in contact with the tester probe Pr0, are selected for testing in correspondence to the combination of switch elements that are turned on. The input/output buffers of the pads under test are deactivated to block their internal current paths. The corresponding switch elements are turned on to connect the off-probe pads under test to the probe pad P0 that is made in contact with the tester probe Pr0, and the leak current of the probes is measured with the tester TS.
摘要翻译： 多总线半导体器件及其探测测试方法基于输入/输出焊盘数压缩测试的方案，处理设备的各个焊盘的DC测试，同时处理足够数量的用于同时测量的设备。 半导体器件包括连接在输入/输出焊盘P 0 -P 4和测试线L 0之间的开关元件SW 0 -SW 4，使得不是非探针焊盘P 1 -P 4中的任意组合的焊盘 与测试仪探头Pr 0接触的选择被选择用于与打开的开关元件的组合相对应的测试。 被测试焊盘的输入/输出缓冲器被禁用以阻止其内部电流路径。 将相应的开关元件接通，将被测试的探针焊盘连接到与测试仪探头Pr 0接触的探针焊盘P 0，并用测试仪TS测量探头的漏电流。
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公开(公告)号：US20050219827A1
公开(公告)日：2005-10-06
申请号：US11091422
申请日：2005-03-29
申请人： Osamu Tateyama , Takeyoshi Hisada , Koichi Sato , Akira Sugiura , Koichi Tsukada
发明人： Osamu Tateyama , Takeyoshi Hisada , Koichi Sato , Akira Sugiura , Koichi Tsukada
CPC分类号： H05K7/20854 , H01L25/165 , H01L2924/0002 , H05K7/209 , Y10T307/977 , H01L2924/00
摘要： An electrical circuit device includes a controller, drivers, and a case. The controller inputs driving signals to the drivers. The drivers have multiple semiconductor relays that turn on and off power supply to electrical loads based on the driving signals. The drivers are housed in the case. The driving signals are transmitted from the controller to the drivers via serial communication. With this configuration, the number of communication lines and the communication connectors and the size of the electrical circuit device are small with respect to parallel communication. When another driver is added, only software modification of the controller and addition of a serial communication line between the controller and the driver are required. Thus, the electrical circuit device can be easily modified for different models of vehicles.
摘要翻译： 电路装置包括控制器，驱动器和壳体。 控制器向驱动器输入驱动信号。 驱动器具有多个半导体继电器，其基于驱动信号来接通和断开电力负载的电源。 司机被安置在案件中。 驱动信号通过串行通信从控制器发送到驱动器。 利用这种配置，通信线路和通信连接器的数量以及电路装置的尺寸相对于并行通信是小的。 当添加另一个驱动程序时，只需要控制器的软件修改和控制器和驱动程序之间的串行通信线路的添加。 因此，对于不同型号的车辆，可以容易地修改电路装置。
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