公开(公告)号：US5324983A

公开(公告)日：1994-06-28

申请号：US902592

申请日：1992-06-22

申请人： Takahiro Onai ,  Takeo Shiba ,  Tohru Nakamura ,  Yoichi Tamaki ,  Katsuyoshi Washio ,  Kazuhiro Ohnishi ,  Masayoshi Saitoh

发明人： Takahiro Onai ,  Takeo Shiba ,  Tohru Nakamura ,  Yoichi Tamaki ,  Katsuyoshi Washio ,  Kazuhiro Ohnishi ,  Masayoshi Saitoh

IPC分类号： H01L21/28 ,  H01L21/331 ,  H01L29/423 ,  H01L29/73 ,  H01L29/732 ,  H01L27/082 ,  H01L27/102 ,  H01L29/00

CPC分类号： H01L29/66272 ,  H01L29/42304

摘要： A first region of a first conductivity type is formed in the surface of a semiconductor body, and second and third regions of a second conductivity type are formed on and under, respectively, of the first region. An electrode region formed on a first insulating film formed on the semiconductor body is connected electrically to the first region. The electrode region is defined as having an elongated first part an upper surface of which is connected to an electrode, and having a second, different part which has a substantially constant width and which width is substantially equal to the thickness of the first portion of the electrode region. A metal silicide film is formed over the upper surface of the first portion of the electrode region. The first, second and third regions can be base, emitter and collector regions, respectively, of a bipolar transistor formed in an island region of an epitaxially grown layer on a semiconductor substrate.

摘要翻译： 第一导电类型的第一区域形成在半导体本体的表面中，并且第二导电类型的第二和第三区域分别形成在第一区域的上下。 形成在形成在半导体主体上的第一绝缘膜上的电极区域与第一区域电连接。 电极区域被限定为具有细长的第一部分，其上表面连接到电极，并且具有第二不同部分，其具有基本恒定的宽度，并且该宽度基本上等于第一部分的厚度 电极区域。 在电极区域的第一部分的上表面上形成金属硅化物膜。 第一，第二和第三区域可以分别是形成在半导体衬底上的外延生长层的岛区中的双极晶体管的基极，发射极和集电极区域。

公开(公告)号：US4926235A

公开(公告)日：1990-05-15

申请号：US106861

申请日：1987-10-13

申请人： Yoichi Tamaki ,  Tokuo Kure ,  Tohru Nakamura ,  Tetsuya Hayashida ,  Kiyoji Ikeda ,  Katsuyoshi Washio ,  Takahiro Onai ,  Akihisa Uchida ,  Kunihiko Watanabe

发明人： Yoichi Tamaki ,  Tokuo Kure ,  Tohru Nakamura ,  Tetsuya Hayashida ,  Kiyoji Ikeda ,  Katsuyoshi Washio ,  Takahiro Onai ,  Akihisa Uchida ,  Kunihiko Watanabe

IPC分类号： H01L21/285 ,  H01L21/763 ,  H01L29/423

CPC分类号： H01L21/763 ,  H01L21/28525 ,  H01L29/42304

摘要： A semiconductor device is disclosed, which includes bipolar transistor each having an emitter, base and collector formed inside each protruding portion of a semiconductor substrate, and trenches for device isolation. The bipolar transistor and the trench are spaced apart from each other by a predetermined spacing. According to this arrangement, the width of a base contact becomes uniform and any change of transistor characteristics can be prevented effectively.

摘要翻译： 公开了一种半导体器件，其包括双极晶体管，每个双极晶体管具有形成在半导体衬底的每个突出部分内的发射极，基极和集电极以及用于器件隔离的沟槽。 双极晶体管和沟槽彼此隔开预定间隔。 根据这种布置，基极接触的宽度变得均匀，并且可以有效地防止晶体管特性的任何变化。

公开(公告)号：US5109263A

公开(公告)日：1992-04-28

申请号：US556365

申请日：1990-07-24

申请人： Mitsuo Nanba ,  Tohru Nakamura ,  Kazuo Nakazato ,  Takeo Shiba ,  Katsuyoshi Washio ,  Kiyoji Ikeda ,  Takahiro Onai ,  Masatada Horiuchi

发明人： Mitsuo Nanba ,  Tohru Nakamura ,  Kazuo Nakazato ,  Takeo Shiba ,  Katsuyoshi Washio ,  Kiyoji Ikeda ,  Takahiro Onai ,  Masatada Horiuchi

IPC分类号： H01L21/331 ,  H01L21/762 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732

CPC分类号： H01L29/66272 ,  H01L21/76229 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/732

摘要： A vertical bipolar transistor arrangement in which the distance between the emitter and the isolation region is kept within a range determined by the sum of emitter depth and base width (i.e., the thickness of the base in the depth direction). This keeps the carriers given by the emitter from getting trapped inside, thereby preventing the cut-off frequency from dropping.

摘要翻译： 发射极和隔离区域之间的距离保持在由发射极深度和基底宽度（即，基底在深度方向上的厚度）确定的范围内的垂直双极晶体管布置。 这样可以防止发射器的载波被捕获到内部，从而防止截止频率的下降。

公开(公告)号：US5237200A

公开(公告)日：1993-08-17

申请号：US833759

申请日：1992-02-11

申请人： Mitsuo Nanba ,  Tohru Nakamura ,  Nakazato Kazuo ,  Takeo Shiba ,  Katsuyoshi Washio ,  Kiyoji Ikeda ,  Takahiro Onai ,  Masatada Horiuchi

发明人： Mitsuo Nanba ,  Tohru Nakamura ,  Nakazato Kazuo ,  Takeo Shiba ,  Katsuyoshi Washio ,  Kiyoji Ikeda ,  Takahiro Onai ,  Masatada Horiuchi

IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L21/762 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732

CPC分类号： H01L29/66272 ,  H01L21/28525 ,  H01L21/76229 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/732

摘要： A vertical bipolar transistor arrangement in which the distance between the emitter and the isolation region is kept within a range determined by the sum of emitter depth and base width (i.e., the thickness of the base in the depth direction). This keeps the carriers given by the emitter from getting trapped inside, thereby preventing the cut-off frequency from dropping.

摘要翻译： 发射极和隔离区域之间的距离保持在由发射极深度和基底宽度（即，基底在深度方向上的厚度）确定的范围内的垂直双极晶体管布置。 这样可以防止发射器的载波被捕获到内部，从而防止截止频率的下降。

公开(公告)号：US5424575A

公开(公告)日：1995-06-13

申请号：US890787

申请日：1992-06-01

申请人： Katsuyoshi Washio ,  Tohru Nakamura ,  Takahiro Onai ,  Masatada Horiuchi ,  Takashi Uchino

发明人： Katsuyoshi Washio ,  Tohru Nakamura ,  Takahiro Onai ,  Masatada Horiuchi ,  Takashi Uchino

IPC分类号： H01L21/331 ,  H01L27/12 ,  H01L29/06 ,  H01L29/73 ,  H01L29/72

CPC分类号： H01L29/7317 ,  H01L27/1203 ,  H01L29/0692

摘要： A semiconductor device has an electrically insulating substrate and a semiconductor layer formed on the insulating substrate. A plurality of semiconductor regions are defined so as to be joined to each other to form at least two homojunctions in the semiconductor layer. A lead conductor for one of the semiconductor regions which is required to have a small thickness has a specific structure such that the lead conductor is in contact with the one semiconductor region at the main surface of the semiconductor layer for electrical connection therebetween and extends over that portion of the semiconductor layer which contributes to definition of at least one of the semiconductor regions other than the first-mentioned one semiconductor region.

摘要翻译： 半导体器件具有形成在绝缘基板上的电绝缘基板和半导体层。 多个半导体区域被定义为彼此接合以在半导体层中形成至少两个同态。 需要具有小厚度的半导体区域之一的引线导体具有特定结构，使得引线导体与半导体层的主表面处的一个半导体区域接触，以在其间进行电连接，并延伸超过该半导体区域 部分半导体层有助于定义除了前述一个半导体区域以外的半导体区域中的至少一个。

公开(公告)号：US5430317A

公开(公告)日：1995-07-04

申请号：US122663

申请日：1993-09-17

申请人： Takahiro Onai ,  Katsuyoshi Washio ,  Tohru Nakamura

发明人： Takahiro Onai ,  Katsuyoshi Washio ,  Tohru Nakamura

IPC分类号： H01L21/331 ,  H01L29/73 ,  H01L29/732 ,  H01L27/01 ,  H01L27/12

CPC分类号： H01L29/66265 ,  H01L29/7317

摘要： A transistor is formed on a bonded SOI substrate. A collector electrode is connected to the peripheral sides of the collector areas on the insulator. A first insulator of isolation is formed on the peripheral side of the collector electrode. A base electrode is connected to a base area on the first insulator of isolation. Second insulators of isolation are formed on the peripheral side of a base electrode, and emitter electrode is connected to an emitter area by the second insulators of isolation. The connections between the collector electrode and the collector areas, between the base electrode and the base area, and between the emitter electrode and the emitter area are made under the emitter electrode, so the occupation area is small.

摘要翻译： 在结合的SOI衬底上形成晶体管。 集电极连接到绝缘体上的集电极区域的周边。 在集电极的周边形成第一隔离绝缘体。 基极连接到第一隔离绝缘体上的基极区域。 隔离的第二绝缘体形成在基极的外围侧，并且发射极通过隔离的第二绝缘体连接到发射极区。 集电极与集电极区域之间，基极电极与基极区域之间以及发射极和发射极区域之间的连接形成在发射电极的下方，占用面积小。

公开(公告)号：US5598015A

公开(公告)日：1997-01-28

申请号：US357342

申请日：1994-12-15

申请人： Tomonori Tanoue ,  Hiroshi Masuda ,  Tohru Nakamura ,  Takahiro Onai ,  Katsuyoshi Washio

发明人： Tomonori Tanoue ,  Hiroshi Masuda ,  Tohru Nakamura ,  Takahiro Onai ,  Katsuyoshi Washio

IPC分类号： H01L29/205 ,  H01L21/331 ,  H01L29/73 ,  H01L29/737 ,  H01L31/0328 ,  H01L27/082 ,  H01L31/0336

CPC分类号： H01L29/66318 ,  H01L29/7371

摘要： A hetero-junction bipolar transistor having an emitter composed of a semiconductor having a wider forbidden band width than that of a semiconductor constituting a base is disclosed. In the transistor, the emitter and the electrode leader area composed of a single crystalline semiconductor are provided being extended from the upper part of the emitter to the surface of the base through an insulating layer, for the purpose of making it possible to miniaturize the transistor and to operate the transistor at a high-speed by decreasing the emitter resistance.

摘要翻译： 公开了一种异质结双极晶体管，其具有由具有比构成基极的半导体宽的禁带宽度的半导体构成的发射极。 在晶体管中，由单晶半导体构成的发射极和电极引出区域通过绝缘层从发射极的上部延伸到基底的表面，以便使晶体管小型化 并通过降低发射极电阻来高速运行晶体管。

公开(公告)号：US06313012B1

公开(公告)日：2001-11-06

申请号：US09303080

申请日：1999-04-30

申请人： Masatada Horiuchi ,  Takahiro Onai ,  Katsuyoshi Washio

发明人： Masatada Horiuchi ,  Takahiro Onai ,  Katsuyoshi Washio

IPC分类号： H01L2130

CPC分类号： H01L27/1203 ,  H01L21/84 ,  Y10S438/977

摘要： Disclosed is an multi-layered SOI substrate, which includes a supporting substrate, and a first insulator, a semiconductor film, a second insulator and a single crystalline semiconductor film (SOI film) which are layered on the main surface of the supporting substrate. The SOI substrate is formed by a direct bonding technique, and a bipolar transistor and an MOS transistor are formed using the single crystalline semiconductor film (SOI layer). The extremely shallow junction can be formed without epitaxial growth, thereby significantly increasing the operation speed of the semiconductor device at a low cost.

摘要翻译： 公开了一种多层SOI衬底，其包括支撑衬底和层叠在支撑衬底的主表面上的第一绝缘体，半导体膜，第二绝缘体和单晶半导体膜（SOI膜）。 SOI衬底通过直接接合技术形成，并且使用单晶半导体膜（SOI层）形成双极晶体管和MOS晶体管。 可以在没有外延生长的情况下形成极浅的结，从而以低成本显着提高半导体器件的操作速度。

公开(公告)号：US6004865A

公开(公告)日：1999-12-21

申请号：US612647

申请日：1996-03-08

申请人： Masatada Horiuchi ,  Takahiro Onai ,  Katsuyoshi Washio

发明人： Masatada Horiuchi ,  Takahiro Onai ,  Katsuyoshi Washio

IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L21/331 ,  H01L21/20 ,  H01L21/336

CPC分类号： H01L27/1203 ,  H01L21/84 ,  Y10S438/977

摘要： Disclosed is an multi-layered SOI substrate, which includes a supporting substrate, and a first insulator, a semiconductor film, a second insulator and a single crystalline semiconductor film (SOI film) which are layered on the main surface of the supporting substrate The SOI substrate is formed by a direct bonding technique, and a bipolar transistor and an MOS transistor are formed using the single crystalline semiconductor film (SOI layer). The extremely shallow junction can be formed without epitaxial growth, thereby significantly increasing the operation speed of the semiconductor device at a low cost.

摘要翻译： 公开了一种多层SOI衬底，其包括支撑衬底和层叠在支撑衬底的主表面上的第一绝缘体，半导体膜，第二绝缘体和单晶半导体膜（SOI膜）。SOI 通过直接接合技术形成衬底，并且使用单晶半导体膜（SOI层）形成双极晶体管和MOS晶体管。 可以在没有外延生长的情况下形成极浅的结，从而以低成本显着提高半导体器件的操作速度。

公开(公告)号：US5962880A

公开(公告)日：1999-10-05

申请号：US892673

申请日：1997-07-14

申请人： Katsuya Oda ,  Eiji Ohue ,  Takahiro Onai ,  Katsuyoshi Washio

发明人： Katsuya Oda ,  Eiji Ohue ,  Takahiro Onai ,  Katsuyoshi Washio

IPC分类号： H01L21/331 ,  H01L29/10 ,  H01L29/737

CPC分类号： H01L29/66242 ,  H01L29/1004 ,  H01L29/7378

摘要： A self-aligned bipolar transistor which has a small base resistance and small emitter-base and collector-base capacitances and is operable at high speed is disclosed. This bipolar transistor is characterized in that a low concentration collector region made of single crystal Si--Ge is self-alignedly formed between an intrinsic base of single crystal Si--Ge and an intrinsic base, and that an extrinsic base electrode and an intrinsic base are connected only through a doped external base. With this arrangement, an energy barrier is not established at the collector base interface owing to the formation of the low concentration region of single crystal Si--Ge, so that the transit time of the carriers charged from the emitter is shortened. The connection between the intrinsic base and the extrinsic base electrode via the doped external base results in the reduction of the base resistance. In addition, the self-aligned formation of the emitter-base-collector leads to the reduction in capacitance between the emitter and the base and also between the collector and the base. Accordingly, a high-speed bipolar transistor can be realized and thus, circuits using the transistor are operable at high speed.

摘要翻译： 公开了具有小的基极电阻和小的发射极基极和集电极基极电容并且可高速操作的自对准双极晶体管。 该双极型晶体管的特征在于，由单晶Si-Ge构成的低浓度集电极区域在单晶Si-Ge的本征基极和本征基极之间自对准地形成，而外部基极电极和固有基极为 仅通过掺杂的外部基极连接。 通过这种布置，由于形成单晶Si-Ge的低浓度区域，在集电极基极界面处没有形成能量势垒，从而缩短了从发射极充电的载流子的渡越时间。 通过掺杂的外部基极的本征基极和外部基极之间的连接导致基极电阻的降低。 此外，发射极 - 基极集电体的自对准形成导致发射极和基极之间以及集电极和基极之间的电容减小。 因此，可以实现高速双极晶体管，因此，使用晶体管的电路可以高速工作。