公开(公告)号：US5286983A

公开(公告)日：1994-02-15

申请号：US962342

申请日：1992-10-16

申请人： Takao Sakamoto ,  Kazuhiro Kobayashi ,  Masahiro Hayama ,  Naoki Nakagawa

发明人： Takao Sakamoto ,  Kazuhiro Kobayashi ,  Masahiro Hayama ,  Naoki Nakagawa

IPC分类号： G02F1/133 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/30 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L27/14

CPC分类号： G02F1/136213 ,  H01L27/12

摘要： A TFT array for a display device includes a plurality of spaced apart gate conductors and a plurality of spaced apart source conductors crossing over the gate conductors. TFT's are arranged in rows and columns. The gates of TFT's in each row are connected to a gate conductor for that row, and the sources of TFT's in each column are connected to a source conductor for that column. The drains of the TFT's are connected to respective pixel electrodes arranged in rows and columns. Each of a plurality of display sections has a storage capacitance connected at one end to an associated pixel electrode. Storage capacitance conductors are arranged parallel to respective gate conductors. Storage capacitors associated with the display sections in each row are connected to a storage capacitance conductor that is connected to the gate conductor of the next adjacent row.

摘要翻译： 用于显示装置的TFT阵列包括多个间隔开的栅极导体和与栅极导体交叉的多个间隔开的源极导体。 TFT以行和列排列。 每列TFT的栅极连接到该行的栅极导体，并且每列中的TFT的源极连接到该列的源极导体。 TFT的漏极连接到以行和列排列的各个像素电极。 多个显示部分中的每一个具有在一端连接到相关联的像素电极的存储电容。 存储电容导体平行于相应的栅极导体布置。 与每行中的显示部分相关联的存储电容器连接到连接到下一相邻行的栅极导体的存储电容导体。

公开(公告)号：US5270845A

公开(公告)日：1993-12-14

申请号：US987591

申请日：1989-12-18

申请人： Hirokazu Sakamoto ,  Masayuki Yokomizo ,  Masahiro Hayama ,  Takao Matsumoto ,  Naoki Nakagawa ,  Makoto Ohtani

发明人： Hirokazu Sakamoto ,  Masayuki Yokomizo ,  Masahiro Hayama ,  Takao Matsumoto ,  Naoki Nakagawa ,  Makoto Ohtani

IPC分类号： G02F1/1362 ,  G02F1/1343

CPC分类号： G02F1/1362 ,  G02F2001/13629

摘要： An improved method for manufacturing a liquid crystal display unit substantially free from gate electrode breakage but with no increase in the number of manufacturing steps over the conventional method. The liquid crystal display unit includes a TFT array substrate including a plurality of gate electrode lines juxtaposed on a transparent insulating substrate, a plurality of source electrode lines arranged across the gate electrode lines, nonlinear active elements disposed at the intersections of the electrode lines, a confronting electrode substrate having a transparent conductive film on the surface thereof confronting the TFT array substrate, and a liquid crystal display material being held between the confronting electrode substrate and the TFT array substrate. Each of the gate electrode lines is constructed in the form of two layers. One of the two layers is made of display electrode material simultaneously with the formation of the display electrode.

摘要翻译： 一种用于制造基本上没有栅电极断裂但是与常规方法相比不增加制造步骤的液晶显示单元的改进方法。 液晶显示单元包括：TFT阵列基板，包括并排在透明绝缘基板上的多个栅极电极线;跨越栅极电极线布置的多个源极电极线;布置在电极线的交点处的非线性有源元件; 在与TFT阵列基板相对的表面上具有透明导电膜的面对电极基板和保持在相对电极基板和TFT阵列基板之间的液晶显示材料。 每个栅电极线以两层的形式构成。 与显示电极的形成同时，两层之一由显示电极材料制成。

公开(公告)号：US5508765A

公开(公告)日：1996-04-16

申请号：US258380

申请日：1994-06-10

申请人： Naoki Nakagawa ,  Satoru Kawamoto ,  Hirokazu Sakamoto ,  Masahiro Hayama

发明人： Naoki Nakagawa ,  Satoru Kawamoto ,  Hirokazu Sakamoto ,  Masahiro Hayama

IPC分类号： G02F1/1343 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/30 ,  H01L21/336 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  G02F1/133

CPC分类号： G02F1/136213

摘要： A matrix-addressed type display device has display material sandwiched between two substrates facing each other, and a transparent pixel electrode disposed in matrix arrangement. The display device display characters by the application of a voltage selectively to the transparent pixel electrode by the use of a thin-film transistor. To improve display characteristics, an electric charge capacitor is provided in each pixel. This electric charge capacitor is connected to an adjacent gate electrode path and includes a transparent inner bottom electrode sandwiched between a dielectric substrate and a transparent pixel electrode. A transparent dielectric film is Interposed between the transparent pixel electrode and the transparent inner bottom electrode.

摘要翻译： 矩阵寻址型显示装置具有夹在彼此面对的两个基板之间的显示材料和以矩阵排列设置的透明像素电极。 显示装置通过使用薄膜晶体管通过选择性地向透明像素电极施加电压来显示字符。 为了改善显示特性，在每个像素中提供电荷电容器。 该电荷电容器连接到相邻的栅电极路径，并且包括夹在电介质基板和透明像素电极之间的透明内底电极。 在透明像素电极和透明内底电极之间插入透明电介质膜。

公开(公告)号：US5066106A

公开(公告)日：1991-11-19

申请号：US296763

申请日：1989-01-13

申请人： Hirokazu Sakamoto ,  Makoto Ohtani ,  Naoki Nakagawa ,  Taro Maejima ,  Masahiro Hayama

发明人： Hirokazu Sakamoto ,  Makoto Ohtani ,  Naoki Nakagawa ,  Taro Maejima ,  Masahiro Hayama

IPC分类号： H01L27/12 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  H01L29/78 ,  H01L29/786

CPC分类号： G02F1/1362 ,  G02F2001/13629 ,  G02F2202/103 ,  G02F2202/104

摘要： A liquid crystal display device includes a transparent conductive film display electrode on a transparent insulating substrate, a plurality of lower layer source conductors disposed simultaneously with a plurality of gate electrode conductors on the substrate, the source conductors intersecting the gate electrode conductors, a gate insulation film on the gate electrode conductors, the lower layer source conductors, and the display electrode, a semiconductor film disposed on the gate insulation film at a position overlying the gate electrode conductors, a drain electrode connected to the display electrode and disposed on the semiconductor film and the gate insulation film, and an upper layer source electrode conductor connected to the lower layer source conductors, the upper layer source electrode conductor disposed on the gate insulation film and the semiconductor film and forming a double-layer structure with the lower layer source conductors.

摘要翻译： 液晶显示装置包括在透明绝缘基板上的透明导电膜显示电极，与基板上的多个栅电极导体同时设置的多个下层源极导体，与栅极导体相交的源极导体，栅极绝缘 在栅极电极导体，下层源极导体和显示电极上形成膜，在覆盖栅极导体的位置配置在栅极绝缘膜上的半导体膜，连接到显示电极并设置在半导体膜上的漏电极 和栅极绝缘膜，以及连接到下层源极导体的上层源极电极导体，设置在栅极绝缘膜和半导体膜上的上层源极电极导体，并与下层源极导体形成双层结构 。

公开(公告)号：US07541646B2

公开(公告)日：2009-06-02

申请号：US11673773

申请日：2007-02-12

申请人： Hitoshi Nagata ,  Takao Sakamoto ,  Naoki Nakagawa

发明人： Hitoshi Nagata ,  Takao Sakamoto ,  Naoki Nakagawa

IPC分类号： H01L21/84

CPC分类号： H01L29/4908 ,  H01L27/1248 ,  H01L29/66757 ,  H01L29/78636

摘要： A thin film transistor device according to an embodiment of the invention includes: a thin film transistor having a silicon layer including a source region, a drain region, and a channel region, a gate insulating layer, and a gate electrode formed on an insulating substrate; an interlayer insulating layer covering the thin film transistor; a line electrically connected with the source region, the drain region, and the gate electrode through a contact hole formed in the interlayer insulating layer; a first upper insulating layer covering the line and the interlayer insulating layer and smoothing out stepped portions of the line and irregularities of a surface of the interlayer insulating layer; and a second upper insulating layer covering the first upper insulating layer, the second upper insulating layer having a hydrogen diffusion coefficient smaller than a hydrogen diffusion coefficient of the first upper insulating layer.

摘要翻译： 根据本发明实施例的薄膜晶体管器件包括：薄膜晶体管，其具有包括源极区，漏极区和沟道区的硅层，栅极绝缘层和形成在绝缘基板上的栅电极 ; 覆盖薄膜晶体管的层间绝缘层; 通过形成在所述层间绝缘层中的接触孔与所述源极区，所述漏极区和所述栅电极电连接的线; 覆盖所述线和所述层间绝缘层的第一上绝缘层，并平滑所述线的台阶部分和所述层间绝缘层的表面的不规则性; 以及覆盖所述第一上绝缘层的第二上绝缘层，所述第二上绝缘层的氢扩散系数小于所述第一上绝缘层的氢扩散系数。

公开(公告)号：US20070210353A1

公开(公告)日：2007-09-13

申请号：US11673773

申请日：2007-02-12

申请人： Hitoshi NAGATA ,  Takao Sakamoto ,  Naoki Nakagawa

发明人： Hitoshi NAGATA ,  Takao Sakamoto ,  Naoki Nakagawa

IPC分类号： H01L29/76 ,  H01L21/8234

CPC分类号： H01L29/4908 ,  H01L27/1248 ,  H01L29/66757 ,  H01L29/78636

摘要： A thin film transistor device according to an embodiment of the invention includes: a thin film transistor having a silicon layer including a source region, a drain region, and a channel region, a gate insulating layer, and a gate electrode formed on an insulating substrate; an interlayer insulating layer covering the thin film transistor; a line electrically connected with the source region, the drain region, and the gate electrode through a contact hole formed in the interlayer insulating layer; a first upper insulating layer covering the line and the interlayer insulating layer and smoothing out stepped portions of the line and irregularities of a surface of the interlayer insulating layer; and a second upper insulating layer covering the first upper insulating layer, the second upper insulating layer having a hydrogen diffusion coefficient smaller than a hydrogen diffusion coefficient of the first upper insulating layer.

摘要翻译： 根据本发明实施例的薄膜晶体管器件包括：薄膜晶体管，其具有包括源极区，漏极区和沟道区的硅层，栅极绝缘层和形成在绝缘基板上的栅电极 ; 覆盖薄膜晶体管的层间绝缘层; 通过形成在所述层间绝缘层中的接触孔与所述源极区，所述漏极区和所述栅电极电连接的线; 覆盖所述线和所述层间绝缘层的第一上绝缘层，并平滑所述线的台阶部分和所述层间绝缘层的表面的不规则性; 以及覆盖所述第一上绝缘层的第二上绝缘层，所述第二上绝缘层的氢扩散系数小于所述第一上绝缘层的氢扩散系数。

公开(公告)号：US07262433B2

公开(公告)日：2007-08-28

申请号：US11137660

申请日：2005-05-26

申请人： Kazuyuki Sugahara ,  Naoki Nakagawa ,  Yoshihiko Toyoda ,  Takao Sakamoto

发明人： Kazuyuki Sugahara ,  Naoki Nakagawa ,  Yoshihiko Toyoda ,  Takao Sakamoto

IPC分类号： H01L27/12

CPC分类号： H01L27/1222 ,  H01L27/1214 ,  H01L27/127 ,  H01L29/78621 ,  H01L29/78627

摘要： A first thin film transistor including a gate electrode, a source region, a drain region, a GOLD region, and a channel region is formed at a first region at a TFT array substrate. A second thin film transistor including a gate electrode, a source region, drain region, a GOLD region, and a channel region is formed at a second region. The GOLD length (0.5 μm) of the GOLD region of the second thin film transistor is set shorter than the GOLD length (1.5 μm) of the GOLD region of the first thin film transistor. Accordingly, a semiconductor device directed to reducing the area occupied by semiconductor elements is obtained.

摘要翻译： 在TFT阵列基板的第一区域形成包括栅极，源极区，漏极区，GOLD区和沟道区的第一薄膜晶体管。 在第二区域形成包括栅电极，源极区，漏极区，GOLD区和沟道区的第二薄膜晶体管。 第二薄膜晶体管的GOLD区域的GOLD长度（0.5μm）被设定为比第一薄膜晶体管的GOLD区域的GOLD长度（1.5μm）短。 因此，获得了旨在减小半导体元件所占的面积的半导体器件。

公开(公告)号：US20050263770A1

公开(公告)日：2005-12-01

申请号：US11137660

申请日：2005-05-26

申请人： Kazuyuki Sugahara ,  Naoki Nakagawa ,  Yoshihiko Toyoda ,  Takao Sakamoto

发明人： Kazuyuki Sugahara ,  Naoki Nakagawa ,  Yoshihiko Toyoda ,  Takao Sakamoto

IPC分类号： H01L51/50 ,  H01L21/336 ,  H01L21/77 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/786 ,  H05B33/14

CPC分类号： H01L27/1222 ,  H01L27/1214 ,  H01L27/127 ,  H01L29/78621 ,  H01L29/78627

摘要： A first thin film transistor including a gate electrode, a source region, a drain region, a GOLD region, and a channel region is formed at a first region at a TFT array substrate. A second thin film transistor including a gate electrode, a source region, drain region, a GOLD region, and a channel region is formed at a second region. The GOLD length (0.5 μm) of the GOLD region of the second thin film transistor is set shorter than the GOLD length (1.5 μm) of the GOLD region of the first thin film transistor. Accordingly, a semiconductor device directed to reducing the area occupied by semiconductor elements is obtained.

摘要翻译： 在TFT阵列基板的第一区域形成包括栅极，源极区，漏极区，GOLD区和沟道区的第一薄膜晶体管。 在第二区域形成包括栅电极，源极区，漏极区，GOLD区和沟道区的第二薄膜晶体管。 第二薄膜晶体管的GOLD区域的GOLD长度（0.5μm）被设定为比第一薄膜晶体管的GOLD区域的GOLD长度（1.5μm）短。 因此，获得了旨在减小半导体元件所占的面积的半导体器件。

公开(公告)号：US20050253195A1

公开(公告)日：2005-11-17

申请号：US11109818

申请日：2005-04-20

申请人： Yoshihiko Toyoda ,  Takao Sakamoto ,  Kazuyuki Sugahara ,  Naoki Nakagawa

发明人： Yoshihiko Toyoda ,  Takao Sakamoto ,  Kazuyuki Sugahara ,  Naoki Nakagawa

IPC分类号： H01L27/08 ,  H01L21/00 ,  H01L21/336 ,  H01L21/77 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L27/127 ,  H01L27/1214 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78645

摘要： A silicon nitride film and a silicon oxide film are formed on a glass substrate. On the silicon oxide film is formed a thin film transistor including a source region, a drain region, a channel region having a predetermined channel length, a GOLD region and an LDD region having an impurity concentration lower than the impurity concentration of the source region, a GOLD region and an LDD region having an impurity concentration lower than the impurity concentration of the drain region, a gate insulation film, and a gate electrode. The gate electrode is formed overlapping with and facing the channel region and the GOLD region. A semiconductor device is obtained, directed to improving source-drain breakdown voltage and AC stress resistance, and achieving desired current property.

摘要翻译： 在玻璃基板上形成氮化硅膜和氧化硅膜。 在氧化硅膜上形成薄膜晶体管，其包括源极区，漏极区，具有预定沟道长度的沟道区，GOLD区和具有低于源区杂质浓度的杂质浓度的LDD区， 具有杂质浓度低于漏区杂质浓度的GOLD区和LDD区，栅极绝缘膜和栅电极。 栅电极与沟道区域和金区域重叠并面对沟道区域。 获得了一种半导体器件，旨在改善源 - 漏击穿电压和AC抗应力，并实现期望的电流特性。

公开(公告)号：US20120112194A1

公开(公告)日：2012-05-10

申请号：US13232251

申请日：2011-09-14

申请人： Takeshi Ono ,  Naoki Nakagawa ,  Yusuke Yamagata ,  Kazunori Inoue ,  Nobuaki Ishiga ,  Kensuke Nagayama ,  Naoki Tsumura ,  Toru Takeguchi

发明人： Takeshi Ono ,  Naoki Nakagawa ,  Yusuke Yamagata ,  Kazunori Inoue ,  Nobuaki Ishiga ,  Kensuke Nagayama ,  Naoki Tsumura ,  Toru Takeguchi

IPC分类号： H01L33/08

CPC分类号： H01L29/458 ,  H01L29/42384 ,  H01L29/66765

摘要： It is an object to provide a technique to improve electric characteristics after a high-temperature treatment even when a high melting point metal barrier layer is not formed. A semiconductor device includes a gate electrode formed on a transparent insulation substrate, a semiconductor layer having a Si semiconductor active film and an ohmic low resistance Si film having an n-type conductivity, being formed in this order on the gate electrode with a gate insulation film interposed between the gate electrode and the semiconductor layer, and the source and drain electrodes directly connected to the semiconductor layer and containing at least aluminum (Al). At least nitrogen (N) is contained in a first region that is in the vicinity of an interface between a side surface of the SI semiconductor active film and the source and drain electrodes.

摘要翻译： 本发明的目的是提供一种即使在没有形成高熔点金属阻挡层的情况下也可以改善高温处理后的电特性的技术。 半导体器件包括形成在透明绝缘基板上的栅极电极，具有Si半导体活性膜的半导体层和具有n型导电性的欧姆低电阻Si膜依次形成在具有栅绝缘层的栅电极上 插入在栅电极和半导体层之间的膜，以及直接连接到半导体层并且至少包含铝（Al）的源极和漏极。 在SI半导体活性膜的侧面与源电极和漏极之间的界面附近的第一区域中至少含有氮（N）。