公开(公告)号：US07179718B2

公开(公告)日：2007-02-20

申请号：US10964614

申请日：2004-10-15

申请人： Takashi Nakamura ,  Tetsu Miyoshi

发明人： Takashi Nakamura ,  Tetsu Miyoshi

IPC分类号： H01L21/30

CPC分类号： C23C4/02 ,  C23C4/185 ,  H01L41/1876 ,  H01L41/314 ,  H01L41/331

摘要： A method of manufacturing a structure in which a substrate can be removed easily from a structure that has been formed on the substrate by using a film forming technology. The method of manufacturing a structure includes the steps of (a) forming an intermediate layer on a substrate; (b) forming a structure including a brittle material layer on the intermediate layer by at least using a spray deposition method of spraying material powder toward the substrate, on which the intermediate layer is formed, to deposit the material powder; and (c) removing the substrate from the structure.

摘要翻译： 通过使用成膜技术，可以容易地从基板上形成的结构体去除基板的结构的制造方法。 制造结构的方法包括以下步骤：（a）在基底上形成中间层; （b）通过至少使用向其上形成有中间层的基板喷射材料粉末的喷镀方法，在中间层上形成包括脆性材料层的结构以沉积材料粉末; 和（c）从结构中去除基底。

公开(公告)号：US20050082662A1

公开(公告)日：2005-04-21

申请号：US10964614

申请日：2004-10-15

申请人： Takashi Nakamura ,  Tetsu Miyoshi

发明人： Takashi Nakamura ,  Tetsu Miyoshi

IPC分类号： C23C4/02 ,  C23C4/18 ,  H01L21/48 ,  H01L23/52 ,  H01L41/24

CPC分类号： C23C4/02 ,  C23C4/185 ,  H01L41/1876 ,  H01L41/314 ,  H01L41/331

摘要： A method of manufacturing a structure in which a substrate can be removed easily from a structure that has been formed on the substrate by using a film forming technology. The method of manufacturing a structure includes the steps of (a) forming an intermediate layer on a substrate; (b) forming a structure including a brittle material layer on the intermediate layer by at least using a spray deposition method of spraying material powder toward the substrate, on which the intermediate layer is formed, to deposit the material powder; and (c) removing the substrate from the structure.

摘要翻译： 通过使用成膜技术，可以容易地从基板上形成的结构体去除基板的结构的制造方法。 制造结构的方法包括以下步骤：（a）在基底上形成中间层; （b）通过至少使用向其上形成有中间层的基板喷射材料粉末的喷雾沉积方法在中间层上形成包括脆性材料层的结构以沉积材料粉末; 和（c）从结构中去除基底。

公开(公告)号：US20050098103A1

公开(公告)日：2005-05-12

申请号：US10964723

申请日：2004-10-15

申请人： Tetsu Miyoshi

发明人： Tetsu Miyoshi

IPC分类号： C23C4/12 ,  C23C24/04 ,  B05C5/00 ,  C23C16/00

CPC分类号： C23C24/04

摘要： In a film forming apparatus according to the aerosol deposition method, the thickness of a structure being formed can be controlled accurately. The film forming apparatus includes an aerosol generating part in which raw material powder is to be provided, a compressed gas cylinder and a pressure regulating part for introducing a gas into the aerosol generating part to blow up the raw material powder thereby generating an aerosol, a substrate holder for holding a substrate on which a structure is to be formed, a nozzle for spraying the aerosol generated in the aerosol generating part toward the substrate, and a sensor to be used for obtaining an amount of primary particles that have contributed to film formation by impinging on the substrate or the structure formed thereon from among the raw material powder contained in the aerosol sprayed from the nozzle.

摘要翻译： 在根据气溶胶沉积法的成膜装置中，可以精确地控制正在形成的结构的厚度。 成膜装置包括将要设置原料粉末的气溶胶发生部分，压缩气瓶和用于将气体引入气溶胶发生部分的压力调节部分，以使原料粉末膨胀从而产生气溶胶， 用于保持要在其上形成结构的基板的基板保持器，用于将在气溶胶发生部分中产生的气溶胶喷射到基板的喷嘴和用于获得有助于成膜的一次粒子的量的传感器 通过从从喷嘴喷射的气溶胶中包含的原料粉末中的基材或其上形成的结构物撞击。

公开(公告)号：US20050179345A1

公开(公告)日：2005-08-18

申请号：US11058282

申请日：2005-02-16

申请人： Tetsu Miyoshi

发明人： Tetsu Miyoshi

IPC分类号： B06B1/06 ,  H01L41/083 ,  H01L41/187 ,  H01L41/22 ,  H01L41/23 ,  H01L41/273 ,  H01L41/293 ,  H01L41/297 ,  H01L41/314 ,  H02N2/00

CPC分类号： H01L41/27 ,  B06B1/064 ,  H01L41/0472 ,  H01L41/083 ,  H01L41/273 ,  H01L41/293 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49128

摘要： An array of piezoelectric elements is easily manufactured by making insulating portions at side surfaces smaller. The piezoelectric element includes: a multilayered structure in which piezoelectric material layers and internal electrode layers are alternately stacked; first insulating films formed by using an AD method, for covering a first group of internal electrode layers at a first surface of the multilayered structure; second insulating films formed by using the AD method, for covering a second group of internal electrode layers at a second surface of the multilayered structure; a first external electrode connected to the second group of internal electrode layers and insulated from the first group of internal electrode layers at the first surface; and a second external electrode connected to the first group of internal electrode layers and insulated from the second group of internal electrode layers at the second surface.

摘要翻译： 通过使侧面的绝缘部较小，容易制造压电元件阵列。 压电元件包括​​：多层结构，其中压电材料层和内部电极层交替堆叠; 通过使用AD方法形成的第一绝缘膜，用于在所述多层结构的第一表面处覆盖第一组内部电极层; 通过使用AD方法形成的第二绝缘膜，用于在多层结构的第二表面处覆盖第二组内部电极层; 第一外部电极，连接到所述第二组内部电极层，并在所述第一表面与所述第一组内部电极层绝缘; 以及第二外部电极，其连接到所述第一组内部电极层并且在所述第二表面处与所述第二组内部电极层绝缘。

公开(公告)号：US06538272B2

公开(公告)日：2003-03-25

申请号：US09534352

申请日：2000-03-24

申请人： Shinobu Yamazaki ,  Kazuya Ishihara ,  Tetsu Miyoshi ,  Jun Kudo

发明人： Shinobu Yamazaki ,  Kazuya Ishihara ,  Tetsu Miyoshi ,  Jun Kudo

IPC分类号： H01L2976

CPC分类号： H01L28/75 ,  H01L21/28568 ,  H01L21/3212 ,  H01L27/10852 ,  H01L28/55

摘要： A contact plug electrically connected with a MOS transistor is formed in a first interlayer dielectric. Then, a barrier metal material is deposited over the first interlayer dielectric and the contact plug, and patterned into a barrier metal electrically connected with the contact plug. After a SiN film is formed as an anti-oxygen-permeation film over the barrier metal and the first interlayer dielectric, the film is abraded by a chemical mechanical polishing technique until a top surface of the barrier metal is exposed. Then, a lower electrode material, a dielectric material and an upper electrode material are deposited in this order on the SiN film and the barrier metal, and then patterned such that a resulting lower electrode covers at least the entire upper surface of the barrier metal. Thereafter a second interlayer dielectric is deposited, and a heat treatment is performed in an oxygen ambient to recover film quality of a capacitor dielectric.

摘要翻译： 在第一层间电介质中形成与MOS晶体管电连接的接触插塞。 然后，将阻挡金属材料沉积在第一层间电介质和接触插塞上，并被图案化成与接触插塞电连接的阻挡金属。 在阻挡金属和第一层间电介质上形成作为抗氧渗透膜的SiN膜之后，通过化学机械抛光技术对该膜进行研磨，直至暴露出阻挡金属的顶表面。 然后，在SiN膜和阻挡金属上依次沉积下电极材料，电介质材料和上电极材料，然后图案化，使得所得的下电极至少覆盖阻挡金属的整个上表面。 此后，沉积第二层间电介质，并在氧环境中进行热处理以恢复电容器电介质的膜质量。

公开(公告)号：US5080907A

公开(公告)日：1992-01-14

申请号：US607743

申请日：1990-10-29

申请人： Takeo Iijima ,  Masaki Otagiri ,  Masao Ueno ,  Tetsu Miyoshi

发明人： Takeo Iijima ,  Masaki Otagiri ,  Masao Ueno ,  Tetsu Miyoshi

IPC分类号： A61K9/00 ,  A61K9/20 ,  A61K9/48 ,  A61K38/01 ,  A61K47/42

CPC分类号： A61K9/0095 ,  A61K38/012 ,  A61K47/42 ,  A61K9/2063 ,  A61K9/4866 ,  Y10S514/801

摘要： Pharmaceutical preparations for oral administration are disclosed which comprise (a) an acidic non-steroidal anti-inflammatory agent having the mean particle size of about 100 .mu.m or less and (b) a protein hydrolyzate or a polypeptide having the mean molecular weight of 4000-12000. The pharmaceutical preparations are in the form of tablets, granules, capsules and dry syrups. They achieve high bioavailability of the anti-inflammatory agent, e.g., ibuprofen.

公开(公告)号：US07673385B2

公开(公告)日：2010-03-09

申请号：US11562253

申请日：2006-11-21

申请人： Tetsu Miyoshi

发明人： Tetsu Miyoshi

IPC分类号： H05K3/30 ,  H01L21/4763

CPC分类号： H01L41/273 ,  H01L41/0471 ,  H01L41/0477 ,  Y10T29/42 ,  Y10T29/49078 ,  Y10T29/49114 ,  Y10T29/49128 ,  Y10T29/4913

摘要： A laminated structure having an electrode hard to peel off and a method of manufacturing the laminated structure. The laminated structure has: a backing substrate; a lower electrode including an adhesive layer containing a metal oxide and a conductive layer formed on the backing substrate with the adhesive layer therebetween; a dielectric layer disposed on the lower electrode; and an upper electrode disposed on the dielectric layer. Further, the method includes the steps of: (a) disposing a lower electrode by forming a conductive layer on a backing substrate with an adhesive layer containing a metal oxide therebetween; (b) disposing a dielectric layer by spraying powder of a dielectric material to the lower electrode for deposition; (c) heat-treating the dielectric layer; and (d) forming an upper electrode on the dielectric layer before or after step (c).

摘要翻译： 具有难以剥离的电极的层叠结构体和层叠结构体的制造方法。 层压结构具有：背衬基板; 包括含有金属氧化物的粘合剂层和形成在背衬基材上的导电层的下部电极，其间具有粘合剂层; 设置在下电极上的电介质层; 以及设置在电介质层上的上电极。 此外，该方法包括以下步骤：（a）通过在背衬基板上形成导电层并且在其间包含金属氧化物的粘合剂层来设置下电极; （b）通过将电介质材料的粉末喷涂到下电极以沉积来设置电介质层; （c）对介电层进行热处理; 和（d）在步骤（c）之前或之后在电介质层上形成上电极。

公开(公告)号：US20070120448A1

公开(公告)日：2007-05-31

申请号：US11604699

申请日：2006-11-28

申请人： Tetsu Miyoshi

发明人： Tetsu Miyoshi

IPC分类号： H01L41/083

CPC分类号： H01L41/083 ,  H01L41/0471 ,  H01L41/0472 ,  H01L41/27 ,  H01L41/314 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49128 ,  Y10T29/49155

摘要： In a multilayered piezoelectric element having a multilayered structure in which electrode layers and piezoelectric material layers are alternately stacked, an internal electrode and a side electrode can be strongly connected. The element includes a first electrode layer having an end portion that protrudes to an outer side than adjacent piezoelectric material layers on a first side surface of the multilayered structure and providing a first insulating region between a second side surface and itself, a second electrode layer having an end portion that protrudes to an outer side than adjacent piezoelectric material layers on the second side surface of the multilayered structure and providing a second insulating region between the first side surface and itself, a first side electrode connected to the end portion of the first electrode layer, and a second side electrode connected to the end portion of the second electrode layer.

摘要翻译： 在具有多层结构的多层压电元件中，其中电极层和压电材料层交替堆叠，可以牢固地连接内部电极和侧面电极。 该元件包括第一电极层，其具有在多层结构的第一侧表面上相对于相邻的压电材料层向外侧突出的端部，并且在第二侧表面和本身之间提供第一绝缘区域，第二电极层具有 在多层结构的第二侧表面上突出到外侧的相邻压电材料层的端部，并且在第一侧表面和本身之间提供第二绝缘区域，连接到第一电极的端部的第一侧电极 以及连接到第二电极层的端部的第二侧电极。

公开(公告)号：US20060103265A1

公开(公告)日：2006-05-18

申请号：US11270528

申请日：2005-11-10

申请人： Tetsu Miyoshi

发明人： Tetsu Miyoshi

IPC分类号： H02N2/00 ,  H01L41/04

CPC分类号： B06B1/0633 ,  A61B8/4494

摘要： A method of manufacturing an ultrasonic transducer array in which plural ultrasonic transducers are arranged on a curved surface with narrow pitches and narrow gaps. The method includes the steps of: (a) preparing a substrate having a curved surface; (b) forming a lower electrode layer on the curved surface of the substrate; (c) forming a piezoelectric material layer on the lower electrode layer; (d) forming an upper electrode layer on the piezoelectric material layer; and (e) forming grooves having predetermined widths with predetermined pitches in a multilayered structure including the lower electrode layer, the piezoelectric material layer and the upper electrode layer formed at steps (b) to (d) so as to form the plural ultrasonic transducers.

摘要翻译： 一种制造超声波换能器阵列的方法，其中多个超声换能器布置在具有窄间距和窄间隙的曲面上。 该方法包括以下步骤：（a）制备具有弯曲表面的基底; （b）在所述基板的弯曲表面上形成下电极层; （c）在下电极层上形成压电材料层; （d）在压电材料层上形成上电极层; 和（e）在包括在步骤（b）至（d）形成的下电极层，压电材料层和上电极层的多层结构中形成具有预定间距的预定宽度的槽，以便形成多个超声换能器。

公开(公告)号：US06335550B1

公开(公告)日：2002-01-01

申请号：US09513084

申请日：2000-02-25

申请人： Tetsu Miyoshi ,  Kazuya Ishihara ,  Takeshi Kijima

发明人： Tetsu Miyoshi ,  Kazuya Ishihara ,  Takeshi Kijima

IPC分类号： H01L2976

CPC分类号： H01L21/28291 ,  H01L29/78391

摘要： A dummy gate electrode is formed just above a channel formation region of a semiconductor substrate by patterning a dummy gate electrode material which is formed on the semiconductor substrate. A dopant is ion-implanted into a surface portion of the semiconductor substrate with the dummy gate electrode used as a mask. Thereby, a source/drain region is formed in self alignment to the dummy gate electrode. A first interlayer insulator is overall formed on the substrate and the dummy gate electrode, and thereafter the first interlayer insulator is subjected to a planarization process to expose a top surface of the dummy gate electrode. A trench is formed on the semiconductor substrate by removing the dummy gate electrode. A gate is made in the trench by forming a buffer dielectric film, a ferroelectric film and a gate electrode material sequentially in this order. Thus, the gate is formed without introduction of any damage in peripheral portions of the trench and without decrease of vertical components of spontaneous polarization in the ferroelectric film.

摘要翻译： 通过对形成在半导体衬底上的虚拟栅极电极材料进行构图来形成虚拟栅电极，正好在半导体衬底的沟道形成区域正上方。 将掺杂剂以伪栅电极作为掩模离子注入到半导体衬底的表面部分中。 由此，源极/漏极区域与伪栅电极自对准形成。 在基板和伪栅电极上整体地形成第一层间绝缘体，然后对第一层间绝缘体进行平坦化处理，以暴露伪栅电极的顶表面。 通过去除虚拟栅电极在半导体衬底上形成沟槽。 通过依次形成缓冲电介质膜，铁电体膜和栅极电极材料，在沟槽中形成栅极。 因此，栅极形成，而不会在沟槽的周边部分中引入任何损坏，并且不会降低铁电体膜中的自发极化的垂直分量。