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    Synchronous semiconductor memory device having set up time of external address signal reduced
    1.
    发明授权
    Synchronous semiconductor memory device having set up time of external address signal reduced 有权
    具有缩短外部地址信号设定时间的同步半导体存储器件

    公开(公告)号：US06026036A

    公开(公告)日：2000-02-15

    申请号：US212308

    申请日：1998-12-16

    申请人： Takashi Sekiya ,  Tomohisa Wada ,  Kunihiko Kozaru

    发明人： Takashi Sekiya ,  Tomohisa Wada ,  Kunihiko Kozaru

    IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C8/06 ,  G11C8/10 ,  G11C11/408 ,  G11C29/04 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C7/225 ,  G11C7/1072 ,  G11C8/06 ,  G11C8/10

    摘要： In a synchronous semiconductor memory device, a predecoder is provided between a former stage address input register formed of first latch circuits and a latter stage address input register formed of second latch circuits. The first and second latch circuits operate in response to first and second internal clock signals complementary to each other. A predecode signal can be latched by the second latch circuit even when the generation of the predecode signal is not in time for the rise of the second internal dock signal due to delay of the input of an external address signal. Accordingly, the set up time for the external address signal can be reduced.

    摘要翻译： 在同步半导体存储器件中，在由第一锁存电路形成的前级地址输入寄存器和由第二锁存电路形成的后级地址输入寄存器之间提供预解码器。 第一和第二锁存电路响应彼此互补的第一和第二内部时钟信号而工作。 即使当由于外部地址信号的输入的延迟而导致第二内部停靠信号的上升，预编码信号的生成不及时时，也可以由第二锁存电路锁存预解码信号。 因此，可以减少外部地址信号的建立时间。

    Semiconductor memory device adaptable to external power supplies of different voltage levels
    2.
    发明授权
    Semiconductor memory device adaptable to external power supplies of different voltage levels 失效
    半导体存储器件适用于不同电压等级的外部电源

    公开(公告)号：US5929539A

    公开(公告)日：1999-07-27

    申请号：US897614

    申请日：1997-07-21

    申请人： Kunihiko Kozaru ,  Tomohisa Wada

    发明人： Kunihiko Kozaru ,  Tomohisa Wada

    IPC分类号： G11C11/413 ,  G05F1/46 ,  G11C5/14 ,  G11C8/08 ,  G11C11/407 ,  H02J1/10

    CPC分类号： G11C5/14 ,  G05F1/465 ,  G11C5/147 ,  G11C8/08 ,  Y10T307/675 ,  Y10T307/696 ,  Y10T307/724 ,  Y10T307/858

    摘要： A semiconductor memory device includes a plurality of external power supply pads P1 to P3. Connection between external power supply pads P1 to P3 and an external power supply is determined in accordance with the voltage of the external power supply to be used, and the connection is switched by bonding. External power supply of a high voltage level is connected to an external power supply pad P2 which is connected to VDC1 and VDC2. A circuit including memory cells operates using the voltage applied from VDC1 or external power supply pad P3, while a group of word line drivers operates using the voltage applied from VDC2 or external power supply pad P1. VDC1 down converts the external power supply voltage, and VDC2 down converts it in accordance with the level of the voltage of the external power supply voltage, and generates internal power supply voltages, respectively. Accordingly, a semiconductor memory device which operates adapted to different external power supplies can be obtained.

    摘要翻译： 半导体存储器件包括多个外部电源焊盘P1至P3。 根据要使用的外部电源的电压来确定外部电源焊盘P1至P3与外部电源之间的连接，并且通过焊接切换连接。 高电压电平的外部电源连接到连接到VDC1和VDC2的外部电源焊盘P2。 包括存储单元的电路使用从VDC1或外部电源焊盘P3施加的电压进行工作，而一组字线驱动器使用从VDC2或外部电源焊盘P1施加的电压进行操作。 VDC1下降转换外部电源电压，VDC2根据外部电源电压的电平降低转换，分别产生内部电源电压。 因此，可以获得适用于不同外部电源的半导体存储器件。

    Semiconductor memory device including a tag memory
    3.
    发明授权
    Semiconductor memory device including a tag memory 失效
    包括标签存储器的半导体存储器件

    公开(公告)号：US5841961A

    公开(公告)日：1998-11-24

    申请号：US487214

    申请日：1995-06-07

    申请人： Kunihiko Kozaru ,  Tomohisa Wada ,  Hirotoshi Sato

    发明人： Kunihiko Kozaru ,  Tomohisa Wada ,  Hirotoshi Sato

    IPC分类号： G06F12/08 ,  G11C29/00 ,  G11C29/04 ,  G06F11/00 ,  G06F11/16

    CPC分类号： G11C29/80 ,  G11C29/808 ,  G11C29/848

    摘要： In repairing a defective memory cell of a data memory placed in a data memory region, a repairing circuit which employs a repairing method causing some access penalty but having high repairing efficiency is located in a redundant row region and a redundant column region in the data memory region. On the other hand, in repairing a defective memory cell of a tag memory placed in a tag memory region, a repairing circuit which employs a repairing method having low repairing efficiency but causing little access penalty is located in a redundant column region in the tag memory region. Accordingly, optimal repair of a defective memory cell can be achieved according to respective functions of the tag memory and the data memory.

    摘要翻译： 在修复放置在数据存储器区域中的数据存储器的有缺陷的存储单元的情况下，采用修复方法引起一些访问损失但具有高修复效率的修复电路位于数据存储器中的冗余行区域和冗余列区域中 地区。 另一方面，在修复放置在标签存储区域中的标签存储器的有缺陷的存储单元的情况下，使用维修效率低但导致小的访问损失的修复方法的修复电路位于标签存储器的冗余列区域中 地区。 因此，可以根据标签存储器和数据存储器的各自的功能来实现对缺陷存储单元的最佳修复。

    Word configuration programmable semiconductor memory with multiple word configuration programming mode
    5.
    发明授权
    Word configuration programmable semiconductor memory with multiple word configuration programming mode 失效
    字配置可编程半导体存储器，具有多字配置编程模式

    公开(公告)号：US6067597A

    公开(公告)日：2000-05-23

    申请号：US780081

    申请日：1996-12-23

    申请人： Kunihiko Kozaru

    发明人： Kunihiko Kozaru

    IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/401 ,  G06F12/00 ,  G11C7/00

    CPC分类号： G11C7/1006 ,  G11C7/1045

    摘要： A semiconductor memory device includes a programming mode detecting circuit for detecting a programming mode, a word configuration programming circuit which can be programmed with a word configuration in the programming mode, and a word configuration selecting circuit for selecting a word configuration based on the programmed word configuration. Therefore, in the semiconductor memory device, a word configuration can be set even after molding.

    摘要翻译： 半导体存储器件包括用于检测编程模式的编程模式检测电路，可在编程模式下用字配置编程的字配置编程电路，以及用于基于编程字选择字配置的字配置选择电路 组态。 因此，在半导体存储装置中，即使在成型后也可以设定字构成。

    Semiconductor memory device internally provided with logic circuit which can be readily controlled and controlling method thereof
    6.
    发明授权
    Semiconductor memory device internally provided with logic circuit which can be readily controlled and controlling method thereof 失效
    半导体存储器件内部设置有可以容易地控制和控制方法的逻辑电路

    公开(公告)号：US06931482B2

    公开(公告)日：2005-08-16

    申请号：US09823996

    申请日：2001-04-03

    申请人： Tadaaki Yamauchi ,  Kunihiko Kozaru

    发明人： Tadaaki Yamauchi ,  Kunihiko Kozaru

    IPC分类号： G11C11/407 ,  G06F12/00 ,  G06F12/02 ,  G09C1/00 ,  G11C7/10 ,  G11C7/24 ,  G11C8/00 ,  G11C11/401 ,  G06F13/00

    CPC分类号： G11C7/1006 ,  G06F12/0223 ,  G06F2212/206 ,  G11C7/24

    摘要： If a region designated by an address signal is a logic control region, an interface portion transmits/receives data to/from a register instead of a DRAM. A data signal used at that time is a control command for a logic circuit held in the register or input data for a process in the logic circuit. Depending on the content held in the register, the logic circuit performs, for example, an encryption process or a process which takes for a microcomputer a long time to complete such as an image processing. The result of processing is stored in the register and read in a sequence of reading from the DRAM.

    摘要翻译： 如果由地址信号指定的区域是逻辑控制区域，则接口部分向/从寄存器而不是DRAM发送/接收数据。 此时使用的数据信号是用于逻辑电路中的处理的寄存器中的逻辑电路的控制命令或输入数据。 根据保存在寄存器中的内容，逻辑电路例如执行诸如图像处理等长时间完成的加密处理或微处理器的处理。 处理结果存储在寄存器中并从DRAM读取的顺序读取。

    Semiconductor memory device capable of reducing power consumption
    7.
    发明授权
    Semiconductor memory device capable of reducing power consumption 失效
    能够降低功耗的半导体存储器件

    公开(公告)号：US5708599A

    公开(公告)日：1998-01-13

    申请号：US691151

    申请日：1996-08-01

    申请人： Hirotoshi Sato ,  Kunihiko Kozaru

    发明人： Hirotoshi Sato ,  Kunihiko Kozaru

    IPC分类号： G11C11/413 ,  G11C11/418 ,  G11C11/419 ,  G11C11/00

    CPC分类号： G11C11/418 ,  G11C11/419

    摘要： A reference voltage generated in a Vref1 generating circuit is supplied from a corresponding applied voltage selector to respective backgates of access transistors in each SRAM cell constituting a column which is selected by a column decoder. On the other hand, a substrate voltage generated in a Vbb generating circuit is supplied from a corresponding applied voltage selector to respective backgates of access transistors in each SRAM cell constituting a column which is not selected by the column decoder.

    摘要翻译： 在Vref1发生电路中产生的参考电压从对应的施加电压选择器提供给构成由列解码器选择的列的每个SRAM单元中的存取晶体管的各个后栅。 另一方面，在Vbb发生电路中产生的衬底电压从相应的施加电压选择器提供给构成未由列解码器选择的列的每个SRAM单元中的存取晶体管的各个后栅。

    Simply interfaced semiconductor integrated circuit device including logic circuitry and embedded memory circuitry operative with a reduced number of pin terminals
    8.
    发明授权
    Simply interfaced semiconductor integrated circuit device including logic circuitry and embedded memory circuitry operative with a reduced number of pin terminals 有权
    简单的接口半导体集成电路器件，包括逻辑电路和嵌入式存储器电路，其操作与减少数量的引脚端子

    公开(公告)号：US06728827B2

    公开(公告)日：2004-04-27

    申请号：US09897978

    申请日：2001-07-05

    申请人： Tadaaki Yamauchi ,  Kunihiko Kozaru

    发明人： Tadaaki Yamauchi ,  Kunihiko Kozaru

    IPC分类号： G06F1300

    CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/1072 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/104

    摘要： An interface circuit performs supply/reception of data with a register instead of supply/reception of data with DRAM when an area specified by an address signal is a logic control area. Data signals in the case are a control command for a logic circuit held in a register and input data to be processed. The logic circuit takes charge of a critical path in processing time such as cryptographic processing and image processing. A processing result is held in the register. The register circuit switches between storage data stored in DRAM and data given from a terminal group to select data to be processed according to a control signal.

    摘要翻译： 当由地址信号指定的区域是逻辑控制区域时，接口电路使用寄存器来执行数据的提供/接收，而不是DRAM的数据提供/接收。 该情况下的数据信号是用于保持在寄存器中的逻辑电路的控制命令和要处理的输入数据。 逻辑电路负责处理时间的关键路径，如加密处理和图像处理。 处理结果保存在寄存器中。 寄存器电路切换存储在DRAM中的存储数据和从终端组给出的数据，以根据控制信号选择要处理的数据。

    Semiconductor memory device and method for reading and writing data therein
    9.
    再颁专利
    Semiconductor memory device and method for reading and writing data therein 失效
    半导体存储器件及其中的数据读写方法

    公开(公告)号：USRE36655E

    公开(公告)日：2000-04-11

    申请号：US917220

    申请日：1997-08-25

    申请人： Kunihiko Kozaru ,  Atsushi Ohba

    发明人： Kunihiko Kozaru ,  Atsushi Ohba

    IPC分类号： G11C11/417 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C7/00

    CPC分类号： G11C7/1051

    摘要： An NAND gate for outputting an output establishment detection signal in response to the fact that a complementary output of a latch type sense amplifier has been established is provided. When a tristate buffer is activated by signal, a word line which has been in a selected state is rendered non-selected state. Accordingly, current can be prevented from leaking from a power supply line to a ground line in tristate buffer. In addition, column current Ic flowing through memory cells can be minimized in response to the fact that word line has been set to a selected state.

    摘要翻译： 提供了一种用于响应于已经建立了锁存型读出放大器的互补输出的事实来输出输出建立检测信号的NAND门。 当通过信号激活三态缓冲器时，已经处于选择状态的字线被呈现为非选择状态。 因此，可以防止电流从三电平缓冲器中的电源线泄漏到接地线。 此外，响应于字线被设置为选择状态的事实，流过存储器单元的列电流Ic可以最小化。

    Semiconductor memory device including improved redundancy circuit
    10.
    发明授权
    Semiconductor memory device including improved redundancy circuit 失效
    半导体存储器件包括改进的冗余电路

    公开(公告)号：US5612917A

    公开(公告)日：1997-03-18

    申请号：US417171

    申请日：1995-04-05

    申请人： Kunihiko Kozaru ,  Koreaki Fujita

    发明人： Kunihiko Kozaru ,  Koreaki Fujita

    IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

    CPC分类号： G11C29/84 ,  G11C29/781

    摘要： A dynamic random access memory includes memory cell array blocks, row decoders, redundant word lines, redundant memory cells, replacement circuits, and a normal memory cell de-select circuit. Each memory cell array block includes normal word lines and normal memory cells. Each row decoder is provided corresponding to one memory cell array block. Any of the redundant word line is provided corresponding to one memory cell array block. Each replacement circuit includes a redundancy select circuit, a replacement address program circuit, and a redundant word line select circuit. The redundancy select circuit has set in advance whether a corresponding redundant word line is to be used or not. The program circuit has an address programmed of a normal word line to be replaced with a corresponding redundant word line. The normal memory cell de-select circuit inactivates a row decoder in response to an output of the replacement circuit when any replacement circuit selects a corresponding redundant word line. When a corresponding redundant word line is not used, a predecode signal is distributed to a program circuit so that the loads of a predecode signal are equal to each other.

    摘要翻译： 动态随机存取存储器包括存储单元阵列块，行解码器，冗余字线，冗余存储单元，替换电路和正常存储单元去选电路。 每个存储单元阵列块包括普通字线和正常存储器单元。 相应于一个存储单元阵列块提供每行解码器。 对应于一个存储单元阵列块提供任何冗余字线。 每个替换电路包括冗余选择电路，替换地址程序电路和冗余字线选择电路。 预先设置了冗余选择电路，是否使用对应的冗余字线。 程序电路具有用相应的冗余字线代替的正常字线编程的地址。 当任何替换电路选择相应的冗余字线时，正常存储单元去选择电路响应于替换电路的输出而使行解码器失活。 当不使用对应的冗余字线时，将预解码信号分配给程序电路，使得预解码信号的负载彼此相等。