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108 条记录 (耗时 0.029 秒)

    Low-power consumption semiconductor memory device
    3.
    发明申请
    Low-power consumption semiconductor memory device 失效
    低功耗半导体存储器件

    公开(公告)号：US20050041514A1

    公开(公告)日：2005-02-24

    申请号：US10949365

    申请日：2004-09-27

    申请人： Takeshi Fujino ,  Kazutami Arimoto ,  Hiroki Shimano

    发明人： Takeshi Fujino ,  Kazutami Arimoto ,  Hiroki Shimano

    IPC分类号： G11C11/405 ,  G11C7/12 ,  G11C11/409 ,  G11C11/4094 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C5/00

    CPC分类号： G11C11/4094 ,  G11C7/12

    摘要： A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.

    摘要翻译： 存储单元单元包括用于彼此存储互补数据的第一存储元件和第二存储元件。 在选择状态下，第一和第二存储元件分别连接到互补位线。 在待机状态下，位线被预充电到对应于存储在存储单元单元中的数据的电压（Vcc或GND）。 可以实现即使在低电源电压下稳定运行的无刷新，低电流消耗的半导体存储器件。

    Low-power consumption semiconductor memory device
    4.
    发明授权
    Low-power consumption semiconductor memory device 失效

    公开(公告)号：US06636454B2

    公开(公告)日：2003-10-21

    申请号：US09756272

    申请日：2001-01-09

    申请人： Takeshi Fujino ,  Kazutami Arimoto ,  Hiroki Shimano

    发明人： Takeshi Fujino ,  Kazutami Arimoto ,  Hiroki Shimano

    IPC分类号： G11C700

    CPC分类号： G11C11/4094 ,  G11C7/12

    摘要： A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.

    Low-power consumption semiconductor memory device
    7.
    发明授权
    Low-power consumption semiconductor memory device 失效
    低功耗半导体存储器件

    公开(公告)号：US06804164B2

    公开(公告)日：2004-10-12

    申请号：US10437281

    申请日：2003-05-14

    申请人： Takeshi Fujino ,  Kazutami Arimoto ,  Hiroki Shimano

    发明人： Takeshi Fujino ,  Kazutami Arimoto ,  Hiroki Shimano

    IPC分类号： G11C700

    CPC分类号： G11C11/4094 ,  G11C7/12

    摘要： A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.

    摘要翻译： 存储单元单元包括用于彼此存储互补数据的第一存储元件和第二存储元件。 在选择状态下，第一和第二存储元件分别连接到互补位线。 在待机状态下，位线被预充电到对应于存储在存储单元单元中的数据的电压（Vcc或GND）。 可以实现即使在低电源电压下稳定运行的无刷新，低电流消耗的半导体存储器件。

    Semiconductor memory device having row-related circuit operating at high speed
    9.
    发明授权
    Semiconductor memory device having row-related circuit operating at high speed 失效
    具有行相关电路的半导体存储器件以高速工作

    公开(公告)号：US06507532B1

    公开(公告)日：2003-01-14

    申请号：US09722687

    申请日：2000-11-28

    申请人： Takeshi Fujino ,  Kazunari Inoue ,  Akira Yamazaki ,  Kazutami Arimoto

    发明人： Takeshi Fujino ,  Kazunari Inoue ,  Akira Yamazaki ,  Kazutami Arimoto

    IPC分类号： G11C800

    CPC分类号： G11C8/12 ,  G11C8/18 ,  G11C11/4087

    摘要： A central row-related control circuit transmits an internal row address signal to each memory sub block in banks of memory mats asynchronously with an external clock signal, and latches a block selection signal for specifying a memory sub block synchronously with an internal clock signal for one clock cycle period for transmission to each memory sub block. A spare determination circuit performs spare determination asynchronously with the clock signal. A semiconductor memory device easily adaptable to bank expansion without increase of the chip area and capable of implementing a high speed access can be provided.

    摘要翻译： 中央行相关控制电路与外部时钟信号异步地将内部行地址信号发送到存储器存储体中的每个存储器子块，并且与一个内部时钟信号同步地锁存用于指定存储器子块的块选择信号 时钟周期，用于传输到每个存储器子块。 备用确定电路与时钟信号异步地执行备用确定。 可以提供容易适应银行扩张的半导体存储器件，而不增加芯片面积并且能够实现高速存取。