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    Self-aligned semiconductor interconnect barrier and manufacturing method therefor
    3.
    发明授权
    Self-aligned semiconductor interconnect barrier and manufacturing method therefor 有权
    自对准半导体互连屏障及其制造方法

    公开(公告)号：US06734559B1

    公开(公告)日：2004-05-11

    申请号：US09663021

    申请日：2000-09-15

    申请人： Kai Yang ,  Takeshi Nogami ,  Dirk Brown ,  Shekhar Pramanick

    发明人： Kai Yang ,  Takeshi Nogami ,  Dirk Brown ,  Shekhar Pramanick

    IPC分类号： H01L2348

    CPC分类号： H01L21/76843 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A self-aligned semiconductor interconnect barrier between channels and vias is provided which is self-aligned and made of a metallic barrier material. A channel is conventionally formed in the semiconductor dielectric, lined with a first metallic barrier material, and filled with a conductive material. A recess is etched to a predetermined depth into the conductive material, and the second metallic barrier material is deposited and removed outside the channel. This leaves the conductive material totally enclosed in metallic barrier material. The metallic barrier material is selected from metals such as tantalum, titanium, tungsten, compounds thereof, alloys thereof, and combinations thereof.

    摘要翻译： 提供通道和通孔之间的自对准半导体互连屏障，其自对准并由金属阻挡材料制成。 通常在半导体电介质中形成通道，衬有第一金属阻挡材料，并填充有导电材料。 将凹陷蚀刻到导电材料中的预定深度，并且将第二金属阻挡材料沉积并移除到通道外。 这使得导电材料完全封闭在金属阻挡材料中。 金属阻隔材料选自钽，钛，钨等金属，其化合物，合金及其组合。

    Test structure used to measure metal bottom coverage in trenches and vias/contacts and method for creating the test structure
    4.
    发明授权
    Test structure used to measure metal bottom coverage in trenches and vias/contacts and method for creating the test structure 失效
    用于测量沟槽和通孔/触点中的金属底部覆盖度的测试结构以及用于创建测试结构的方法

    公开(公告)号：US06380556B1

    公开(公告)日：2002-04-30

    申请号：US09619292

    申请日：2000-07-19

    申请人： David Bang ,  Takeshi Nogami ,  Guarionex Morales ,  Shekhar Pramanick

    发明人： David Bang ,  Takeshi Nogami ,  Guarionex Morales ,  Shekhar Pramanick

    IPC分类号： H01L2940

    CPC分类号： H01L22/14 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A test structure used to measure metal bottom coverage in semiconductor integrated circuits. The metal is deposited in etched trenches, vias and/or contacts created during the integrated circuit manufacturing process. A predetermined pattern of probe contacts are disposed about the semiconductor wafer. Metal deposited in the etched areas is heated to partially react with the underlying and surrounding undoped material. The remaining unreacted metal layer is then removed, and an electrical current is applied to the probe contacts. The resistance of the reacted portion of metal and undoped material is measured to determine metal bottom coverage. Some undoped material may also be removed to measure metal sidewall coverage. The predetermined pattern of probe contacts is preferably arranged in a Kelvin or Vander Paaw structure.

    摘要翻译： 用于测量半导体集成电路中金属底部覆盖的测试结构。 金属沉积在集成电路制造过程中产生的蚀刻沟槽，通孔和/或触点中。 探针触点的预定图案围绕半导体晶片设置。 沉积在蚀刻区域中的金属被加热以部分地与下面的和周围的未掺杂材料反应。 然后去除剩余的未反应的金属层，并且将电流施加到探针接触件。 测量金属和未掺杂材料的反应部分的电阻以确定金属底部覆盖。 还可以去除一些未掺杂的材料以测量金属侧壁覆盖。 探针接触件的预定图案优选地以开尔文或范德瓦结构布置。

    Method of forming reliable capped copper interconnects
    5.
    发明授权
    Method of forming reliable capped copper interconnects 失效
    形成可靠封盖铜互连的方法

    公开(公告)号：US06492266B1

    公开(公告)日：2002-12-10

    申请号：US09112158

    申请日：1998-07-09

    申请人： Minh Van Ngo ,  Shekhar Pramanick ,  Takeshi Nogami

    发明人： Minh Van Ngo ,  Shekhar Pramanick ,  Takeshi Nogami

    IPC分类号： H01L2144

    CPC分类号： H01L21/76862 ,  H01L21/76801 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10S438/902 ,  Y10S438/906 ,  H01L2924/00

    摘要： The adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member: (a) under plasma conditions with ammonia and silane or dichlorosilane to form a copper silicide layer thereon; or (b) with an ammonia plasma followed by reaction with silane or dichlorosilane to form a copper silicide layer thereon. The diffusion barrier layer is then deposited on the copper suicide layer. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric interlayer, chemical mechanical polishing, then treating the exposed surface of the Cu/Cu alloy interconnect to form the copper silicide layer thereon, and depositing a silicon nitride diffusion barrier layer on the copper silicide layer.

    摘要翻译： 扩散阻挡层或覆盖层对Cu或Cu合金互连构件的粘附通过处理Cu或Cu合金互连构件的暴露表面而显着增强：（a）在等离子体条件下用氨和硅烷或二氯硅烷形成铜 硅化物层; 或（b）与氨等离子体接触，然后与硅烷或二氯硅烷反应，在其上形成硅化铜层。 然后将扩散阻挡层沉积在硅化硅层上。 实施例包括电镀或化学镀Cu或Cu合金以填充介电中间层中的镶嵌开口，化学机械抛光，然后处理Cu / Cu合金互连的暴露表面以在其上形成硅化铜层，并沉积氮化硅 扩散阻挡层在硅化铜层上。

    Prevention of inter-channel current leakage in semiconductors
    6.
    发明授权
    Prevention of inter-channel current leakage in semiconductors 有权
    防止半导体中的沟道间漏电

    公开(公告)号：US06465345B1

    公开(公告)日：2002-10-15

    申请号：US09321643

    申请日：1999-05-28

    申请人： Takeshi Nogami ,  Shekhar Pramanick

    发明人： Takeshi Nogami ,  Shekhar Pramanick

    IPC分类号： H01L214763

    CPC分类号： H01L21/76885 ,  H01L21/31116 ,  H01L21/3185 ,  H01L21/3212 ,  H01L21/76834 ,  H01L21/7684

    摘要： A method for eliminating copper atomic residue from the channel oxide layer on semiconductors after chemical-mechanical polishing is provided. After chemical-mechanical polishing, the silicon oxide is plasma etched to remove its surface and any residue. After plasma etching, an etch stop layer of silicon nitride is deposited by chemical-vapor deposition. Both the plasma etch of the silicon dioxide and the chemical-vapor deposition of the silicon nitride can be performed in the same vacuum chamber in the same semiconductor processing tool with only a change of the gas mixture.

    摘要翻译： 提供了一种在化学机械抛光后从半导体上的沟道氧化物层除去铜原子残留物的方法。 在化学机械抛光后，氧化硅被等离子体蚀刻以除去其表面和任何残留物。 在等离子体蚀刻之后，通过化学气相沉积沉积氮化硅的蚀刻停止层。 二氧化硅的等离子体蚀刻和氮化硅的化学气相沉积都可以在相同的半导体加工工具中的相同的真空室中进行，只有气体混合物的变化。

    Copper metalization with improved electromigration resistance
    8.
    发明授权
    Copper metalization with improved electromigration resistance 有权
    铜金属化具有改善的电迁移率

    公开(公告)号：US06214731B1

    公开(公告)日：2001-04-10

    申请号：US09442771

    申请日：1999-11-18

    申请人： Takeshi Nogami ,  Minh Van Ngo ,  Shekhar Pramanick

    发明人： Takeshi Nogami ,  Minh Van Ngo ,  Shekhar Pramanick

    IPC分类号： H01L2144

    CPC分类号： H01L21/76856 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Cu interconnection patterns with improved electromigration resistance are formed by depositing a barrier metal layer, such as W or WN, to line an opening in a dielectric layer. The exposed surface of the deposited barrier metal layer is treated with silane or dichlorosaline to form a thin silicon layer thereon. Cu is then deposited to fill the opening and reacted with the thin silicon layer to form a thin layer of Cu silicide at the interface between Cu and the barrier metal layer, thereby reducing the interface defect density and improving electromigration resistance.

    摘要翻译： 具有改善的电迁移电阻的Cu互连图案通过沉积阻挡金属层（例如W或WN）来形成，以对电介质层中的开口进行排列。 沉积的阻挡金属层的暴露表面用硅烷或二氯苯胺处理以在其上形成薄硅层。 然后沉积Cu以填充开口并与薄硅层反应以在Cu和阻挡金属层之间的界面处形成Cu硅化物的薄层，从而降低界面缺陷密度并提高电迁移阻力。

    Semiconductor device having an intermetallic layer on metal interconnects
    9.
    发明授权
    Semiconductor device having an intermetallic layer on metal interconnects 有权
    在金属互连上具有金属间层的半导体器件

    公开(公告)号：US06172421B2

    公开(公告)日：2001-01-09

    申请号：US09132282

    申请日：1998-08-11

    申请人： Paul Raymond Besser ,  Shekhar Pramanick ,  Takeshi Nogami ,  Subhash Gupta

    发明人： Paul Raymond Besser ,  Shekhar Pramanick ,  Takeshi Nogami ,  Subhash Gupta

    IPC分类号： H01L2348

    CPC分类号： H01L21/76858 ,  H01L21/76849 ,  H01L21/76886

    摘要： The present invention relates to the formation of a protective intermetallic layer 15 on the surface of damascene metal interconnects 12 during semiconductor fabrication. The intermetallic layer 15 prevents problems associated with formation of an oxide layer on the surface of the interconnect. The intermetallic layer is formed by depositing a metal on the surface of the interconnect that will both reduce any present metal oxide layer and form an intermetallic with the interconnect metal.

    摘要翻译： 本发明涉及在半导体制造期间在镶嵌金属互连件12的表面上形成保护性金属间化合物层15。 金属间层15防止与互连表面上形成氧化物层有关的问题。 金属间化合物层通过在互连表面上沉积金属而形成，该金属将既减少任何存在的金属氧化物层并与互连金属形成金属间化合物。

    Method of reliably capping copper interconnects
    10.
    发明授权
    Method of reliably capping copper interconnects 有权
    铜互连可靠封盖的方法

    公开(公告)号：US6165894A

    公开(公告)日：2000-12-26

    申请号：US131872

    申请日：1998-08-10

    申请人： Shekhar Pramanick ,  Takeshi Nogami ,  Minh Van Ngo

    发明人： Shekhar Pramanick ,  Takeshi Nogami ,  Minh Van Ngo

    IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

    CPC分类号： H01L21/76886 ,  H01L21/76834 ,  H01L21/76862 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member with an ammonia plasma followed by depositing the diffusion barrier layer on the treated surface. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric interlayer, chemical mechanical polishing, treating the exposed surface of the Cu/Cu alloy interconnect with an ammonia plasma, and depositing a silicon nitride diffusion barrier layer directly on the plasma treated surface.

    摘要翻译： 通过用氨等离子体处理Cu或Cu合金互连构件的暴露表面，然后在经处理的表面上沉积扩散阻挡层，扩散阻挡层或覆盖层对Cu或Cu合金互连构件的粘附性显着增强。 实施例包括电镀或化学镀Cu或Cu合金以填充介电中间层中的镶嵌开口，化学机械抛光，用氨等离子体处理Cu / Cu合金互连的暴露表面，并直接沉积氮化硅扩散阻挡层 在等离子体处理的表面上。