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    Semiconductor integrated circuit for liquid crystal display driver
    1.
    发明申请
    Semiconductor integrated circuit for liquid crystal display driver 审中-公开
    半导体集成电路用于液晶显示驱动

    公开(公告)号：US20060132417A1

    公开(公告)日：2006-06-22

    申请号：US11311161

    申请日：2005-12-20

    申请人： Takeshi Shigenobu ,  Mitsuru Hiraki ,  Masashi Horiguchi ,  Kazuo Okado ,  Takesada Akiba

    发明人： Takeshi Shigenobu ,  Mitsuru Hiraki ,  Masashi Horiguchi ,  Kazuo Okado ,  Takesada Akiba

    IPC分类号： G09G3/36

    CPC分类号： G09G3/3696 ,  G09G3/3674 ,  G09G3/3685

    摘要： In a liquid crystal drive controller formed as a semiconductor integrated circuit having therein a power source circuit including a boosting circuit and driving a source line and a gate line of a TFT liquid crystal panel, the number of external capacitive elements and the number of external terminals for connecting the external capacitive elements are reduced, thereby reducing the size and cost of the chip and an electronic device on which the chip is mounted. As a boosting circuit for generating a voltage for driving a source line of the TFT liquid crystal panel in the liquid crystal controller having therein the power source including the boosting circuit, a boosting circuit having an external capacitive element is used. On the other hand, as a boosting circuit for generating a voltage for driving a gate line, a charge pump having a built-in (on-chip) capacitive element is used.

    摘要翻译： 在形成为半导体集成电路的液晶驱动控制器中，其中具有包括升压电路并驱动TFT液晶面板的源极线和栅极线的电源电路，外部电容元件的数量和外部端子的数量 用于连接外部电容元件的功能减小，从而减小芯片的尺寸和成本以及安装芯片的电子设备。 作为用于在其中具有包括升压电路的电源的液晶控制器中产生用于驱动TFT液晶面板的源极线的电压的升压电路，使用具有外部电容元件的升压电路。 另一方面，作为用于产生用于驱动栅极线的电压的升压电路，使用具有内置（片上）电容元件的电荷泵。

    Voltage generation circuit and semiconductor integrated circuit device
    2.
    发明申请
    Voltage generation circuit and semiconductor integrated circuit device 审中-公开
    电压发生电路和半导体集成电路器件

    公开(公告)号：US20070164809A1

    公开(公告)日：2007-07-19

    申请号：US10584395

    申请日：2004-12-02

    申请人： Keiko Fukuda ,  Mitsuru Hiraki ,  Masashi Horiguchi ,  Takesada Akiba ,  Shuzo Ichiki ,  Hideki Tsunoda ,  Akihiro Kitagawa

    发明人： Keiko Fukuda ,  Mitsuru Hiraki ,  Masashi Horiguchi ,  Takesada Akiba ,  Shuzo Ichiki ,  Hideki Tsunoda ,  Akihiro Kitagawa

    IPC分类号： G05F1/10

    CPC分类号： G05F3/30

    摘要： A constant current is formed by supplying voltage differences between bases and emitters of a first transistor which allows a first current to flow in the emitter thereof and a second transistor which allows a second current having a current density larger than a current density of the first transistor to flow in an emitter thereof to a first resistance. A second resistance is provided on a ground potential side of a circuit in series with the first resistance. A third and a fourth resistances are provided between collectors and the power supply voltages of the first transistor and the second transistor. Both collector voltages of the first and second transistors are supplied to a differential amplifier circuit having the CMOS constitution thus forming an output voltage and, at the same time, the output voltage is supplied to bases of the first transistor and the second transistor in common.

    摘要翻译： 通过提供允许第一电流在其发射极中流动的第一晶体管的基极和发射极之间的电压差而形成恒定电流，以及第二晶体管，其允许具有大于第一晶体管的电流密度的电流密度的第二电流 在其发射体中流动到第一阻力。 在与第一电阻串联的电路的地电位侧设置第二电阻。 集电器和第一晶体管和第二晶体管的电源电压之间提供第三和第四电阻。 第一和第二晶体管的集电极电压都被提供给具有CMOS结构的差分放大器电路，从而形成输出电压，并且同时将输出电压共同地提供给第一晶体管和第二晶体管的基极。

    Semiconductor memory circuit
    3.
    发明授权
    Semiconductor memory circuit 有权
    半导体存储电路

    公开(公告)号：US07821862B2

    公开(公告)日：2010-10-26

    申请号：US11902877

    申请日：2007-09-26

    申请人： Takesada Akiba ,  Shigeki Ueda ,  Toshikazu Tachibana ,  Masashi Horiguchi

    发明人： Takesada Akiba ,  Shigeki Ueda ,  Toshikazu Tachibana ,  Masashi Horiguchi

    IPC分类号： G11C5/14 ,  G11C8/00

    CPC分类号： G11C5/147 ,  G11C11/4074 ,  G11C2207/2227

    摘要： The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.

    摘要翻译： 本发明提供了一种半导体存储器电路，其能够在配备有共享使用电源，地址信号和数据总线的多个芯片的系统中减少非操作时的电流消耗。 半导体存储器电路具有内部电路，其能够选择性地通过开关装置执行工作电压的供应和停止，并且包括存储器阵列。 在其中接收预定控制信号的输入电路通过开关装置控制供电和停止工作电压，以便在不进行存储器操作时减小直流电流和泄漏电流，由此可以实现低功耗。

    Semiconductor memory circuit
    4.
    发明申请
    Semiconductor memory circuit 有权

    公开(公告)号：US20060239103A1

    公开(公告)日：2006-10-26

    申请号：US11472252

    申请日：2006-06-22

    申请人： Takesada Akiba ,  Shigeki Ueda ,  Toshikazu Tachibana ,  Masashi Horiguchi

    发明人： Takesada Akiba ,  Shigeki Ueda ,  Toshikazu Tachibana ,  Masashi Horiguchi

    IPC分类号： G11C5/14

    CPC分类号： G11C5/147 ,  G11C11/4074 ,  G11C2207/2227

    摘要： The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.

    Semiconductor integrated circuit device
    6.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US5448526A

    公开(公告)日：1995-09-05

    申请号：US282311

    申请日：1994-07-29

    申请人： Masashi Horiguchi ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Goro Kitsukawa ,  Takayuki Kawahara ,  Takesada Akiba

    发明人： Masashi Horiguchi ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Goro Kitsukawa ,  Takayuki Kawahara ,  Takesada Akiba

    IPC分类号： G01R31/317 ,  G05F3/24 ,  G11C5/14 ,  G11C13/00

    CPC分类号： G11C5/147 ,  G01R31/31715 ,  G05F3/24

    摘要： An intermediate voltage generating circuit for generating a voltage lying between an external power supply voltage and a ground voltage, and two voltage limiter circuits for generating internal power supply voltages and stabilized with this intermediate voltage as a reference are provided in a semiconductor integrated circuit. Even if the external power supply voltage or the ground voltage fluctuates, no disagreement is produced between a logical threshold of a circuit operating on the external power supply voltage and a logical threshold of a circuit operating on the internal power supply voltage.

    摘要翻译： 在半导体集成电路中设置有用于产生位于外部电源电压和接地电压之间的电压的中间电压产生电路和用于产生内部电源电压并以该中间电压稳定的两个限压器电路。 即使外部电源电压或接地电压发生波动，也不会在外部电源电压工作的电路的逻辑阈值与内部电源电压的电路的逻辑阈值之间产生不同意见。

    Semiconductor integrated circuit device
    9.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US5289425A

    公开(公告)日：1994-02-22

    申请号：US870460

    申请日：1992-04-17

    申请人： Masashi Horiguchi ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Goro Kitsukawa ,  Takayuki Kawahara ,  Takesada Akiba

    发明人： Masashi Horiguchi ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Goro Kitsukawa ,  Takayuki Kawahara ,  Takesada Akiba

    IPC分类号： G01R31/317 ,  G05F3/24 ,  G11C5/14 ,  G11C8/00

    CPC分类号： G11C5/147 ,  G01R31/31715 ,  G05F3/24

    摘要： An intermediate voltage generating circuit for generating a voltage lying between an external power supply voltage and a ground voltage, and two voltage limiter circuits for generating internal power supply voltages and stabilized with this intermediate voltage as a reference are provided in a semiconductor integrated circuit. Even if the external power supply voltage or the ground voltage fluctuates, no disagreement is produced between a logical threshold of a circuit operating on the external power supply voltage and a logical threshold of a circuit operating on the internal power supply voltage.

    摘要翻译： 在半导体集成电路中设置有用于产生位于外部电源电压和接地电压之间的电压的中间电压产生电路和用于产生内部电源电压并以该中间电压稳定的两个限压器电路。 即使外部电源电压或接地电压发生波动，也不会在外部电源电压工作的电路的逻辑阈值与内部电源电压的电路的逻辑阈值之间产生不同意见。

    Semiconductor memory circuit
    10.
    发明授权
    Semiconductor memory circuit 有权
    半导体存储电路

    公开(公告)号：US08223577B2

    公开(公告)日：2012-07-17

    申请号：US13067857

    申请日：2011-06-30

    申请人： Takesada Akiba ,  Shigeki Ueda ,  Toshikazu Tachibana ,  Masashi Horiguchi

    发明人： Takesada Akiba ,  Shigeki Ueda ,  Toshikazu Tachibana ,  Masashi Horiguchi

    IPC分类号： G11C8/00

    CPC分类号： G11C5/147 ,  G11C11/4074 ,  G11C2207/2227

    摘要： The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.

    摘要翻译： 本发明提供了一种半导体存储器电路，其能够在配备有共享使用电源，地址信号和数据总线的多个芯片的系统中减少非操作时的电流消耗。 半导体存储器电路具有内部电路，其能够选择性地通过开关装置执行工作电压的供应和停止，并且包括存储器阵列。 在其中接收预定控制信号的输入电路通过开关装置控制供电和停止工作电压，以便在不进行存储器操作时减小直流电流和泄漏电流，由此可以实现低功耗。