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公开(公告)号：US6107869A
公开(公告)日：2000-08-22
申请号：US96456
申请日：1998-06-11
IPC分类号： G11C11/41 , G11C5/14 , G11C8/08 , G11C11/401 , G11C11/407 , G11C11/409 , H01L21/3205 , H01L21/822 , H01L21/8242 , H01L23/52 , H01L27/04 , H01L27/108 , G05F3/02
CPC分类号： G11C8/08 , G11C5/14 , G11C5/147 , H01L2924/0002
摘要： It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.
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2.发明授权Semiconductor integrated circuit including first and second switching transistors having operation states corresponding to operation states of first and second logic circuits 有权包括具有对应于第一和第二逻辑电路的操作状态的操作状态的第一和第二开关晶体管的半导体集成电路公开(公告)号：US07199648B2
公开(公告)日：2007-04-03
申请号：US10859141
申请日：2004-06-03
IPC分类号： G05F1/10
CPC分类号： G11C8/08 , G11C5/14 , G11C5/147 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit is provided having first and second logic circuits coupled to first and second sub-power supply lines, respectively. First and second switching transistors are also provided to connect the first and second sub-power supply lines to a main power supply line. The first and second switching transistors are kept off in an operation stop state of the first and second logic circuits, and are kept on in operable state of the first and second logic circuits.
摘要翻译： 提供半导体集成电路，其具有分别耦合到第一和第二子电源线的第一和第二逻辑电路。 还提供第一和第二开关晶体管以将第一和第二子电源线连接到主电源线。 第一和第二开关晶体管被保持在第一和第二逻辑电路的操作停止状态，并且保持在第一和第二逻辑电路的可操作状态。
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公开(公告)号：US06747509B2
公开(公告)日：2004-06-08
申请号：US10045105
申请日：2002-01-15
IPC分类号： G05F110
CPC分类号： G11C8/08 , G11C5/14 , G11C5/147 , H01L2924/0002 , H01L2924/00
摘要： It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.
摘要翻译： 可以减小副电源线上的电压降，以降低亚阈值电流，从而防止逻辑电路的工作速度降低。 主电源线沿着包括其亚阈值电流必须减小的MOS逻辑电路的矩形区域的一侧布置，并且在垂直于主电源线的方向上的区域上布置多个子电源线。 用于将副电源线选择性地电连接到主电源线的多个开关MOS晶体管相对于主电源线分散布置。 通过相对于主电源线分散配置开关MOS晶体管，与在一个地方设置开关MOS晶体管的情况相比，可以降低副电源线的等效电阻。
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公开(公告)号：US06339358B1
公开(公告)日：2002-01-15
申请号：US09513929
申请日：2000-02-28
IPC分类号： G05F110
CPC分类号： G11C8/08 , G11C5/14 , G11C5/147 , H01L2924/0002 , H01L2924/00
摘要： It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.
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5.发明授权
公开(公告)号：US5274601A
公开(公告)日：1993-12-28
申请号：US972545
申请日：1992-11-06
申请人： Takayuki Kawahara , Yoshiki Kawajiri , Takesada Akiba , Masashi Horiguchi , Takao Watanabe , Goro Kitsukawa , Yasushi Kawase , Toshikazu Tachibana , Masakazu Aoki
发明人： Takayuki Kawahara , Yoshiki Kawajiri , Takesada Akiba , Masashi Horiguchi , Takao Watanabe , Goro Kitsukawa , Yasushi Kawase , Toshikazu Tachibana , Masakazu Aoki
CPC分类号： H03K19/0016 , G11C5/14 , G11C8/08
摘要： A device parameter of a switching transistor is set in such a way that a leakage current of the switching transistor making up a power source switch which is turned off in a stand-by state is smaller than the sum total of subthreshold currents of P-channel or N-channel MOS transistors in an off state of a plurality of CMOS circuits. Therefore, the currents which flow through the plurality of CMOS circuits in the stand-by state are not determined by the subthreshold current but are determined by a small leakage current of the switching transistor. As a result, even when the CMOS circuit is shrunken and the subthreshold current increases, it is possible to reduce the current consumption in the stand-by state.
摘要翻译： 开关晶体管的器件参数被设置为使得构成在待机状态下被截止的电源开关的开关晶体管的漏电流小于P沟道的亚阈值电流的总和 或多个CMOS电路处于断开状态的N沟道MOS晶体管。 因此，在待机状态下流过多个CMOS电路的电流不由亚阈值电流确定，而是由开关晶体管的小的漏电流确定。 结果，即使当CMOS电路收缩并且亚阈值电流增加时，也可以减少待机状态下的电流消耗。
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公开(公告)号：US5983358A
公开(公告)日：1999-11-09
申请号：US938962
申请日：1997-09-26
申请人： Masashi Horiguchi , Shinichi Miyatake , Tathunori Mushya , Yasuhiro Kasama , Yoichi Matsuno , Yasushi Kawase , Yoshinobu Nakagome
发明人： Masashi Horiguchi , Shinichi Miyatake , Tathunori Mushya , Yasuhiro Kasama , Yoichi Matsuno , Yasushi Kawase , Yoshinobu Nakagome
IPC分类号： G11C11/401 , G06F11/00 , G11C29/00 , G11C29/04
CPC分类号： G11C29/842
摘要： A semiconductor memory having a redundancy circuit includes a judgment device for receiving outputs of first ROMs for storing a defective address therein and judging whether or not a defective memory cell and a spare memory cell to replace the defective memory cell belong to the same memory cell, and also includes a timing adjustment circuit for changing the timing of control signals applied to memory mat control circuits according to an output of the judgment device. When the defective and spare memory cells belong to the same memory mat, the timing of the control signals is made fast.
摘要翻译： 具有冗余电路的半导体存储器包括判断装置，用于接收用于存储缺陷地址的第一ROM的输出，并判断有缺陷的存储单元和备用存储单元是否属于同一个存储单元， 并且还包括定时调整电路，用于根据判断装置的输出来改变施加到存储器垫控制电路的控制信号的定时。 当有缺陷的和备用的存储器单元属于相同的存储器存储器时，控制信号的定时变得快。
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公开(公告)号：US20060267903A1
公开(公告)日：2006-11-30
申请号：US11441166
申请日：2006-05-26
申请人： Yasushi Kawase , Susumu Ishida , Takesada Akiba , Yasushi Nagata , Naoki Miyamoto , Kazuyoshi Shiba
发明人： Yasushi Kawase , Susumu Ishida , Takesada Akiba , Yasushi Nagata , Naoki Miyamoto , Kazuyoshi Shiba
IPC分类号： G09G3/36
CPC分类号： G09G3/3655 , G09G5/005 , G09G2310/08 , H01L27/0207 , H01L27/11521 , H01L27/11558 , H01L29/42324 , H01L29/42328 , H01L29/7885
摘要： The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits.
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8.发明授权公开(公告)号：US07826264B2
公开(公告)日：2010-11-02
申请号：US11441166
申请日：2006-05-26
申请人： Yasushi Kawase , Susumu Ishida , Takesada Akiba , Yasushi Nagata , Naoki Miyamoto , Kazuyoshi Shiba
发明人： Yasushi Kawase , Susumu Ishida , Takesada Akiba , Yasushi Nagata , Naoki Miyamoto , Kazuyoshi Shiba
IPC分类号： G11C11/34
CPC分类号： G09G3/3655 , G09G5/005 , G09G2310/08 , H01L27/0207 , H01L27/11521 , H01L27/11558 , H01L29/42324 , H01L29/42328 , H01L29/7885
摘要： The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits.
摘要翻译： 本发明实现了一种用于驱动液晶（液晶控制驱动器IC）的半导体集成电路器件，其能够根据要使用的液晶显示器的规格容易地设定驱动条件等。 在用于驱动液晶显示器的半导体集成电路器件中提供电可编程非易失性存储器电路（EPROM）或电可擦除和可编程的非易失性存储器电路（EEPROM），并将设置信息存储在存储器电路中。 存储电路由与其他电路的形成器件的半导体制造工艺相同的工艺形成的普通器件构成。
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公开(公告)号：USRE38944E1
公开(公告)日：2006-01-24
申请号：US09974962
申请日：2001-10-12
IPC分类号： G11C8/00
CPC分类号： H01L27/10805 , G11C7/10 , G11C11/408 , G11C11/4096 , G11C11/4097 , H01L27/105
摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and columns selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.
摘要翻译： 具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。 每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。 子存储垫以格子排列。 子存储垫上面是：主字线和列选择信号线与正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有 间距，是子位线的间距的整数倍; 以及选择性地连接指定的子公共I / O线的主要公共I / O线。
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公开(公告)号：US5966341A
公开(公告)日：1999-10-12
申请号：US982398
申请日：1997-12-02
IPC分类号： G11C11/401 , G11C7/10 , G11C11/407 , G11C11/408 , G11C11/409 , G11C11/4096 , G11C11/4097 , H01L21/8242 , H01L27/105 , H01L27/108 , G11C13/00
CPC分类号： H01L27/10805 , G11C11/408 , G11C11/4096 , G11C11/4097 , G11C7/10 , H01L27/105
摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.
摘要翻译： 具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。 每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。 子存储垫以格子排列。 在子存储器衬垫之上是与主要字线和列选择信号线正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有 间距，是子位线的间距的整数倍; 以及选择性地连接指定的子公共I / O线的主要公共I / O线。
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