公开(公告)号：US07997939B2

公开(公告)日：2011-08-16

申请号：US12845504

申请日：2010-07-28

申请人： Taku Akaiwa ,  Susumu Shinozaki ,  Takeshi Matsuda ,  Tatsuo Kato ,  Masaji Komuro ,  Kenji Nakazawa ,  Kenji Hatano ,  Yoshitaka Kimura

发明人： Taku Akaiwa ,  Susumu Shinozaki ,  Takeshi Matsuda ,  Tatsuo Kato ,  Masaji Komuro ,  Kenji Nakazawa ,  Kenji Hatano ,  Yoshitaka Kimura

IPC分类号： H01R24/04

CPC分类号： H01R24/58 ,  H01R24/66 ,  H01R2107/00

摘要： A plug includes a plug housing and a metal terminal group. The metal terminal group includes a mating electrode group on the first end side thereof and a connection electrode group on the second end side, the mating electrode group including mating electrode sections that are disposed with an insulating resin interposed therebetween and are to be in contact with the contacts of a mating jack, the connection electrode group including connection electrode sections that are disposed with an insulating resin interposed therebetween and are connected to the electrodes of a connection member. The mating electrode sections are disposed coaxially with an axis P of the plug, and at least two of the connection electrode sections are disposed around the axis P so as to surround the axis P side by side.

摘要翻译： 插头包括插头壳体和金属端子组。 金属端子组包括在其第一端侧的配合电极组和第二端侧的连接电极组，所述配合电极组包括配置有绝缘树脂的配合电极部，并且与第 配合插座的触点，连接电极组包括连接电极部分，该连接电极部分设置有绝缘树脂并且连接到连接部件的电极。 配合电极部分与插头的轴线P同轴设置，并且至少两个连接电极部分围绕轴线P设置成围绕轴线P并排。

公开(公告)号：US5556292A

公开(公告)日：1996-09-17

申请号：US410034

申请日：1995-03-23

申请人： Tatsuo Kato ,  Katsuhiko Kishi ,  Takeshi Matsuda

发明人： Tatsuo Kato ,  Katsuhiko Kishi ,  Takeshi Matsuda

IPC分类号： H01B7/00 ,  H01R27/00

CPC分类号： H01R13/052 ,  H01R24/40 ,  H01R2103/00 ,  H01R9/05

摘要： A cable connector includes a plug for connecting a coaxial cable to an electronic device such as a television or video cassette recorder. The plug includes a sleeve that connects with a first grounding terminal of a receptacle. An outer diameter of the sleeve is dimensioned to provide a good unstressed interference fit with the first grounding terminal. The sleeve has slits in a portion to permit elastic deformation when connecting with a second grounding terminal having an inner diameter less than that of the first grounding terminal. These slits permit the sleeve to compress sufficiently to form an interference fit inside the second grounding terminal. When both the first grounding terminal of the receptacle and the sleeve of the plug are dimensioned for the PAL format, and the second grounding terminal is dimensioned for the SECAM format, the plug fits either grounding terminal.

摘要翻译： 电缆连接器包括用于将同轴电缆连接到诸如电视或录像机的电子设备的插头。 插头包括与插座的第一接地端子连接的套筒。 套筒的外径的尺寸被设计成提供与第一接地端子良好的不受应力的过盈配合。 当与具有小于第一接地端子的内径的第二接地端子连接时，套筒在一部分中具有狭缝以允许弹性变形。 这些狭缝允许套筒充分压缩以在第二接地端子内形成干涉配合。 当插座的第一个接地端子和插头的套管均为PAL格式，第二个接地端子的尺寸为SECAM格式时，插头适合接地端子。

公开(公告)号：US07586371B2

公开(公告)日：2009-09-08

申请号：US11589140

申请日：2006-10-30

申请人： Suguru Tachibana ,  Kenta Aruga ,  Tatsuo Kato

发明人： Suguru Tachibana ,  Kenta Aruga ,  Tatsuo Kato

IPC分类号： H03F3/45

CPC分类号： H03F3/45475 ,  H03F3/347 ,  H03F3/45183 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2203/45138 ,  H03F2203/45466

摘要： The present invention is contrived to adopt a differential pair type amplifier circuit comprising a differential pair constituted by a first transistor receiving an input of a first signal and by a second transistor receiving an input of a third signal generated by outputting a second signal of which the voltage level is a power supply voltage. Elements requiring a matching are two transistors constituting the differential pair for the amplifier circuit. Because of this, the elements requiring a matching can be placed close to each other regardless of a layout between the amplifier circuits.

摘要翻译： 本发明被设计为采用差分对型放大器电路，其包括由接收第一信号的输入的第一晶体管和由第二晶体管构成的差分对，所述第二晶体管接收通过输出第二信号而产生的第三信号的输入， 电压电平是电源电压。 需要匹配的元件是构成放大器电路的差分对的两个晶体管。 因此，不管放大器电路之间的布局如何，需要匹配的元件可以彼此靠近放置。

公开(公告)号：US07479767B2

公开(公告)日：2009-01-20

申请号：US11704952

申请日：2007-02-12

申请人： Tatsuo Kato

发明人： Tatsuo Kato

IPC分类号： G05F1/613 ,  G05F3/16

CPC分类号： G05F1/56

摘要： A power supply step-down circuit is adapted to a semiconductor integrated circuit having a first operation mode and a second operation mode having a smaller current consumption than the first operation mode. The power supply step-down circuit includes a first step-down circuit activated only during the first operation mode to step down an input power supply voltage to an output voltage, a second step-down circuit provided integrally with the first step-down circuit and activated only during the second operation mode to step down the input power supply voltage to an output voltage, an output terminal to output the output voltage of one of the first and second step-down circuits that is activated, and an output circuit to maintain the output voltage that is output from the output terminal lower than the input power supply voltage for a first predetermined time when an operation mode makes a transition from the first operation mode to the second operation mode.

摘要翻译： 电源降压电路适用于具有比第一操作模式小的电流消耗的第一操作模式和第二操作模式的半导体集成电路。 电源降压电路包括仅在第一操作模式期间激活的第一降压电路，以将输入电源电压降压为输出电压;第二降压电路，与第一降压电路整体设置;以及 仅在第二操作模式期间激活以将输入电源电压降低到输出电压，输出端子输出被激活的第一和第二降压电路中的一个的输出电压，以及输出电路，以维持 当操作模式从第一操作模式转换到第二操作模式时，从输出端子输出低于输入电源电压的输出电压达到第一预定时间。

公开(公告)号：US20070040600A1

公开(公告)日：2007-02-22

申请号：US11260176

申请日：2005-10-28

申请人： Suguru Tachibana ,  Kazuhiro Mitsuda ,  Tatsuo Kato

发明人： Suguru Tachibana ,  Kazuhiro Mitsuda ,  Tatsuo Kato

IPC分类号： G05F1/10

CPC分类号： G05F3/30

摘要： A band gap circuit includes a voltage generating circuit, and a first and a second switched capacitor circuits (SCC). Operational amplifier in the first and the second SCC are connected though a coupling capacitor. Capacitance of the coupling capacitor is smaller than that of a feedback capacitor in the first SCC. A PTAT voltage is obtained by multiplying a thermal voltage by a coefficient determined based on capacitances of input capacitors and feedback capacitors in each of the first and the second SCC, and the coupling capacitor. The voltage generating circuit generates a forward bias voltage that has a negative temperature-dependency at a p-n junction. The PTAT voltage is added to the forward bias voltage to generate a reference voltage independent of temperature.

摘要翻译： 带隙电路包括电压产生电路和第一和第二开关电容器电路（SCC）。 第一和第二SCC中的运算放大器通过耦合电容器连接。 耦合电容的电容小于第一SCC中的反馈电容的电容。 通过将热电压乘以基于第一和第二SCC中的每一个中的输入电容器和反馈电容器的电容确定的系数和耦合电容器来获得PTAT电压。 电压产生电路产生在p-n结处具有负温度依赖性的正向偏置电压。 将PTAT电压加到正向偏置电压以产生独立于温度的参考电压。

公开(公告)号：US07176740B2

公开(公告)日：2007-02-13

申请号：US10948524

申请日：2004-09-24

申请人： Suguru Tachibana ,  Tatsuo Kato

发明人： Suguru Tachibana ,  Tatsuo Kato

IPC分类号： H03L5/00

CPC分类号： H03K3/356113 ,  H03K17/102 ,  H03K17/223

摘要： A level conversion circuit that prevents the operation speed from decreasing when the power supply voltage decreases while appropriately performing level conversion. The level conversion circuit includes first and second PMOS transistors. A first NMOS transistor is connected to the first PMOS transistor and the second PMOS transistor. A second NMOS transistor is connected to the second PMOS transistor and the first PMOS transistor. A bias circuit, connected to the first and second NMOS transistors, generates a bias potential that is supplied to the first and second NMOS transistors and that is greater than the first voltage by a threshold voltage of the first and second NMOS transistors. The bias circuit further controls current, which determines the bias potential and flows to the bias circuit, in accordance with a control signal having the first voltage.

摘要翻译： 电平转换电路，在适当进行电平转换的同时，防止电源电压下降时的运转速度降低。 电平转换电路包括第一和第二PMOS晶体管。 第一NMOS晶体管连接到第一PMOS晶体管和第二PMOS晶体管。 第二NMOS晶体管连接到第二PMOS晶体管和第一PMOS晶体管。 连接到第一和第二NMOS晶体管的偏置电路产生提供给第一和第二NMOS晶体管并且大于第一电压的第一和第二NMOS晶体管的阈值电压的偏置电位。 偏置电路还根据具有第一电压的控制信号控制电流，该电流确定偏置电位并流向偏置电路。

公开(公告)号：US20050237099A1

公开(公告)日：2005-10-27

申请号：US10948524

申请日：2004-09-24

申请人： Suguru Tachibana ,  Tatsuo Kato

发明人： Suguru Tachibana ,  Tatsuo Kato

IPC分类号： H03M1/14 ,  H03K3/356 ,  H03K17/10 ,  H03K17/22 ,  H03K19/0185 ,  H03M9/00

CPC分类号： H03K3/356113 ,  H03K17/102 ,  H03K17/223

摘要： A level conversion circuit that prevents the operation speed from decreasing when the power supply voltage decreases while appropriately performing level conversion. The level conversion circuit includes first and second PMOS transistors. A first NMOS transistor is connected to the first PMOS transistor and the second PMOS transistor. A second NMOS transistor is connected to the second PMOS transistor and the first PMOS transistor. A bias circuit, connected to the first and second NMOS transistors, generates a bias potential that is supplied to the first and second NMOS transistors and that is greater than the first voltage by a threshold voltage of the first and second NMOS transistors. The bias circuit further controls current, which determines the bias potential and flows to the bias circuit, in accordance with a control signal having the first voltage.

摘要翻译： 电平转换电路，在适当进行电平转换的同时，防止电源电压下降时的运转速度降低。 电平转换电路包括第一和第二PMOS晶体管。 第一NMOS晶体管连接到第一PMOS晶体管和第二PMOS晶体管。 第二NMOS晶体管连接到第二PMOS晶体管和第一PMOS晶体管。 连接到第一和第二NMOS晶体管的偏置电路产生提供给第一和第二NMOS晶体管并且大于第一电压的第一和第二NMOS晶体管的阈值电压的偏置电位。 偏置电路还根据具有第一电压的控制信号控制电流，该电流确定偏置电位并流向偏置电路。

公开(公告)号：US20050052303A1

公开(公告)日：2005-03-10

申请号：US10774525

申请日：2004-02-10

申请人： Suguru Tachibana ,  Tatsuo Kato ,  Hideo Nunokawa

发明人： Suguru Tachibana ,  Tatsuo Kato ,  Hideo Nunokawa

IPC分类号： H03M1/38 ,  H03K5/08 ,  H03M1/00 ,  H03M1/46 ,  H03M1/66

CPC分类号： H03M1/002 ,  H03M1/468

摘要： An AD converter includes a sample-&-hold circuit which samples and holds an input analog potential in a first period, and generates a signal indicative of a magnitude relation between the held input analog potential and a reference potential in a second period, a plurality of amplifiers connected in series which amplify an output of the sample-&-hold circuit, and a control circuit which controls operating timing of the amplifiers so as to make at least one of the amplifiers start operating in a middle of the first period.

摘要翻译： AD转换器包括采样保持电路，其在第一周期中采样并保持输入模拟电位，并且产生指示在第二周期中保持的输入模拟电位与参考电位之间的大小关系的信号，多个 放大器连接的放大器，其放大采样保持电路的输出;以及控制电路，其控制放大器的工作时序，以使至少一个放大器在第一周期的中间开始工作。

公开(公告)号：US5338792A

公开(公告)日：1994-08-16

申请号：US63761

申请日：1993-05-20

申请人： Yasushi Nagase ,  Masami Kobayashi ,  Tatsuo Kato ,  Shinichi Imuta

发明人： Yasushi Nagase ,  Masami Kobayashi ,  Tatsuo Kato ,  Shinichi Imuta

IPC分类号： C08L23/20 ,  C08J5/18 ,  C08L23/18 ,  C08J5/10

CPC分类号： C08J5/18 ,  C08L23/20 ,  C08J2323/20 ,  Y10T428/31504

摘要： The improved heat-resistant overwrap film is formed from a resin composition that comprises (A) 98-70 parts by weight of a 4-methyl-1-pentene based polymer, (B) 1-15 parts by weight of an isobutylene based polymer having a kinematic viscosity of 2-5000 cSt at 100.degree. C., and (C) 1-15 parts by weight of a butene-1 based solid polymer, with the sum of (A)+(B)+(C) being 100 parts by weight. The film is excellent in heat resistance, flexibility, tackiness and transparency.

摘要翻译： 改进的耐热外包膜由包含（A）98-70重量份的4-甲基-1-戊烯基聚合物的树脂组合物形成，（B）1-15重量份的异丁烯基聚合物 在100℃下运动粘度为2-5000cSt，（C）1-15重量份丁烯-1系固体聚合物，（A）+（B）+（C）之和为 100重量份。 该膜具有优异的耐热性，柔韧性，粘性和透明度。

公开(公告)号：US20100156533A1

公开(公告)日：2010-06-24

申请号：US12535184

申请日：2009-08-04

申请人： Suguru Tachibana ,  Kenta Aruga ,  Tatsuo Kato

发明人： Suguru Tachibana ,  Kenta Aruga ,  Tatsuo Kato

IPC分类号： H03F3/45

CPC分类号： H03F3/45475 ,  H03F3/347 ,  H03F3/45183 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2203/45138 ,  H03F2203/45466

摘要： The present invention is contrived to adopt a differential pair type amplifier circuit comprising a differential pair constituted by a first transistor receiving an input of a first signal and by a second transistor receiving an input of a third signal generated by outputting a second signal of which the voltage level is a power supply voltage. Elements requiring a matching are two transistors constituting the differential pair for the amplifier circuit. Because of this, the elements requiring a matching can be placed close to each other regardless of a layout between the amplifier circuits.

摘要翻译： 本发明被设计为采用差分对型放大器电路，其包括由接收第一信号的输入的第一晶体管和由第二晶体管构成的差分对，所述第二晶体管接收通过输出第二信号而产生的第三信号的输入， 电压电平是电源电压。 需要匹配的元件是构成放大器电路的差分对的两个晶体管。 因此，不管放大器电路之间的布局如何，需要匹配的元件可以彼此靠近放置。