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公开(公告)号：US06495883B2
公开(公告)日：2002-12-17
申请号：US10060379
申请日：2002-02-01
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/4232 , H01L29/42368 , H01L29/4238
摘要： A semiconductor device has a dielectric strength for a gate oxide film at a trench bottom that is higher than that of side walls used for channels. An n+0 type substrate 1 having substrate plane orientation of (110) is prepared, and the side walls of a trench where channels are formed are in (100) planes. The other, non-channel forming, side walls of the trench are in (110) planes. Thus, the growth rate of the gate oxide film 7 in the non-channel forming side walls and the trench bottom is faster than that in the channel forming side walls. As a result, the film thickness at the non-channel-forming side walls and the trench bottom is greater than that of the channel-forming side walls. Accordingly, the device has high mobility, and there is no drop of dielectric strength due to partial reduction of the thickness of the gate oxide film 7. This achieves both a reduction of the ON resistance and an increase in the dielectric strength of the semiconductor device.
摘要翻译： 半导体器件在沟槽底部具有比用于沟道的侧壁高的栅极氧化膜的介电强度。 制备具有（110）基板平面取向的n + 0型基板1，并且形成通道的沟槽的侧壁在（100）平面中。 沟槽的另一个非通道形成侧壁在（110）平面中。 因此，非通道形成侧壁和沟槽底部中的栅极氧化膜7的生长速度比形成沟道的侧壁的生长速度快。 结果，在非沟道形成侧壁和沟槽底部处的膜厚度大于沟道形成侧壁的膜厚度。 因此，器件具有高迁移率，并且由于栅极氧化膜7的厚度的部分减小而不会降低介电强度。这实现了导通电阻的降低和半导体器件的介电强度的增加 。
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公开(公告)号：US07364980B2
公开(公告)日：2008-04-29
申请号：US11539441
申请日：2006-10-06
IPC分类号： H01L21/76
CPC分类号： C30B25/165 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/0634
摘要： Closure at the opening of a trench with an epitaxial film is restrained, and thereby, filling morphology in the trenches is improved. A method for manufacturing a semiconductor substrate includes a step for growing an epitaxial layer 11 on the surface of a silicon substrate 13, a step of forming a trench 14 in this epitaxial layer, and a step of filling the inside of the trench 14 with the epitaxial film 12, wherein mixed gas made by mixing halogenoid gas into silicon source gas is circulated as material gas in filling the inside of the trench with the epitaxial film, and when the standard flow rate of the halogenoid gas is defined as Xslm and the film formation speed of the epitaxial film formed by the circulation of the silicon source gas is defined as Yμm/min, in the case when the aspect ratio of the trench is less than 10, an expression Y
摘要翻译： 在具有外延膜的沟槽的开口处的闭合被抑制，从而提高了沟槽中的填充形态。 一种制造半导体衬底的方法包括在硅衬底13的表面上生长外延层11的步骤，在该外延层中形成沟槽14的步骤，以及将沟槽14内部填充的步骤 外延膜12，其中通过将卤素气体混入硅源气体而制成的混合气体作为原料气体循环，用外延膜填充沟槽内部，当将卤化物气体的标准流量定义为Xslm时，膜 通过硅源气体的循环形成的外延膜的形成速度定义为Ymum / min，在沟槽的纵横比小于10的情况下，满足表达式Y <0.2X + 0.10，在 沟槽的纵横比在10以上且小于20的情况下，满足表达式Y <0.2X + 0.05，在沟槽的纵横比为20以上的情况下，表达式Y <0.2× 满意
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公开(公告)号：US20070082455A1
公开(公告)日：2007-04-12
申请号：US11539441
申请日：2006-10-06
IPC分类号： H01L21/76
CPC分类号： C30B25/165 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/0634
摘要： Closure at the opening of a trench with an epitaxial film is restrained, and thereby, filling morphology in the trenches is improved. A method for manufacturing a semiconductor substrate includes a step for growing an epitaxial layer 11 on the surface of a silicon substrate 13, a step of forming a trench 14 in this epitaxial layer, and a step of filling the inside of the trench 14 with the epitaxial film 12, wherein mixed gas made by mixing halogenoid gas into silicon source gas is circulated as material gas in filling the inside of the trench with the epitaxial film, and when the standard flow rate of the halogenoid gas is defined as Xslm and the film formation speed of the epitaxial film formed by the circulation of the silicon source gas is defined as Yμm/min, in the case when the aspect ratio of the trench is less than 10, an expression Y
摘要翻译： 在具有外延膜的沟槽的开口处的闭合被抑制，从而提高了沟槽中的填充形态。 一种制造半导体衬底的方法包括在硅衬底13的表面上生长外延层11的步骤，在该外延层中形成沟槽14的步骤，以及将沟槽14内部填充的步骤 外延膜12，其中通过将卤素气体混入硅源气体而制成的混合气体作为原料气体循环，用外延膜填充沟槽内部，当将卤化物气体的标准流量定义为Xslm时，膜 通过硅源气体的循环形成的外延膜的形成速度定义为Ymum / min，在沟槽的纵横比小于10的情况下，满足表达式Y <0.2X + 0.10，在 沟槽的纵横比在10以上且小于20的情况下，满足表达式Y <0.2X + 0.05，在沟槽的纵横比为20以上的情况下，表达式Y <0.2× 满意
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4.发明授权公开(公告)号：US07811907B2
公开(公告)日：2010-10-12
申请号：US11528678
申请日：2006-09-28
IPC分类号： H01L29/78 , H01L29/12 , H01L21/336 , H01L21/205
CPC分类号： H01L29/7813 , H01L21/02381 , H01L21/0243 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L29/045 , H01L29/0634 , H01L29/66734 , H01L29/7811
摘要： A method for manufacturing a semiconductor device includes steps of: forming a trench on a main surface of a silicon substrate; forming a first epitaxial film on the main surface and in the trench; and forming a second epitaxial film on the first epitaxial film. The step of forming the first epitaxial film has a first process condition with a first growth rate of the first epitaxial film. The step of forming the second epitaxial film has a second process condition with a second growth rate of the second epitaxial film. The second growth rate is larger than the first growth rate.
摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在硅衬底的主表面上形成沟槽; 在主表面和沟槽中形成第一外延膜; 以及在所述第一外延膜上形成第二外延膜。 形成第一外延膜的步骤具有第一外延膜的第一生长速率的第一工艺条件。 形成第二外延膜的步骤具有第二外延膜的第二生长速率的第二工艺条件。 第二增长率大于第一增长率。
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5.发明申请公开(公告)号：US20070072397A1
公开(公告)日：2007-03-29
申请号：US11526879
申请日：2006-09-26
IPC分类号： H01L21/20
CPC分类号： H01L29/66712 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/02639 , H01L21/823487 , H01L29/0615 , H01L29/0634 , H01L29/1095 , H01L29/7811 , H01L29/7813
摘要： A method for manufacturing a semiconductor device includes steps of: forming a first epitaxial film on a silicon substrate; forming a trench in the first epitaxial film; and forming a second epitaxial film on the first epitaxial film and in the trench. The step of forming the second epitaxial film includes a final step, in which a mixed gas of a silicon source gas and a halide gas is used. The silicon substrate has an arsenic concentration defined as α. The second epitaxial film has an impurity concentration defined as β. The arsenic concentration and the impurity concentration has a relationship of: α≦3×33 109×ln(β)−1×1021.
摘要翻译： 一种制造半导体器件的方法包括以下步骤：在硅衬底上形成第一外延膜; 在所述第一外延膜中形成沟槽; 以及在所述第一外延膜和所述沟槽中形成第二外延膜。 形成第二外延膜的步骤包括使用硅源气体和卤化物气体的混合气体的最后步骤。 硅衬底的砷浓度定义为α。 第二外延膜具有定义为β的杂质浓度。 砷浓度和杂质浓度具有以下关系：α<= 3×33×10×（β）-1×10 21。
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公开(公告)号：US20070032092A1
公开(公告)日：2007-02-08
申请号：US11496708
申请日：2006-08-01
IPC分类号： H01L21/311 , H01L21/31 , H01L21/469
CPC分类号： H01L21/28525 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/28562 , H01L29/045 , H01L29/0634 , H01L29/66734
摘要： A method for manufacturing a semiconductor device includes steps of: forming a trench on a semiconductor substrate, which is made of silicon; and filling the trench with an epitaxial layer. The epitaxial layer is made of silicon, and the step of filling the trench includes a step of performing a plasma CVD method with using a silicon source gas. By using anisotropic character of a plasma, the epitaxial layer is selectively deposited on a bottom of the trench. Thus, the trench is filled with the epitaxial layer having no void.
摘要翻译： 一种制造半导体器件的方法包括以下步骤：在由硅制成的半导体衬底上形成沟槽; 并用外延层填充沟槽。 外延层由硅制成，填充沟槽的步骤包括使用硅源气体进行等离子体CVD法的步骤。 通过使用等离子体的各向异性特征，外延层选择性地沉积在沟槽的底部。 因此，沟槽被无空隙的外延层填充。
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7.发明授权公开(公告)号：US07642178B2
公开(公告)日：2010-01-05
申请号：US11526879
申请日：2006-09-26
IPC分类号： H01L21/00
CPC分类号： H01L29/66712 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/02639 , H01L21/823487 , H01L29/0615 , H01L29/0634 , H01L29/1095 , H01L29/7811 , H01L29/7813
摘要： A method for manufacturing a semiconductor device includes steps of: forming a first epitaxial film on a silicon substrate; forming a trench in the first epitaxial film; and forming a second epitaxial film on the first epitaxial film and in the trench. The step of forming the second epitaxial film includes a final step, in which a mixed gas of a silicon source gas and a halide gas is used. The silicon substrate has an arsenic concentration defined as α. The second epitaxial film has an impurity concentration defined as β. The arsenic concentration and the impurity concentration has a relationship of: α≦3×1019×ln(β)−1×1021.
摘要翻译： 一种制造半导体器件的方法包括以下步骤：在硅衬底上形成第一外延膜; 在所述第一外延膜中形成沟槽; 以及在所述第一外延膜和所述沟槽中形成第二外延膜。 形成第二外延膜的步骤包括使用硅源气体和卤化物气体的混合气体的最后步骤。 硅衬底的砷浓度定义为α。 第二外延膜具有定义为β的杂质浓度。 砷浓度和杂质浓度具有以下关系：α<= 3×10 19×ln（β）-1×10 21。
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公开(公告)号：US07517771B2
公开(公告)日：2009-04-14
申请号：US11496708
申请日：2006-08-01
IPC分类号： H01L21/76
CPC分类号： H01L21/28525 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/28562 , H01L29/045 , H01L29/0634 , H01L29/66734
摘要： A method for manufacturing a semiconductor device includes steps of: forming a trench on a semiconductor substrate, which is made of silicon; and filling the trench with an epitaxial layer. The epitaxial layer is made of silicon, and the step of filling the trench includes a step of performing a plasma CVD method with using a silicon source gas. By using anisotropic character of a plasma, the epitaxial layer is selectively deposited on a bottom of the trench. Thus, the trench is filled with the epitaxial layer having no void.
摘要翻译： 一种制造半导体器件的方法包括以下步骤：在由硅制成的半导体衬底上形成沟槽; 并用外延层填充沟槽。 外延层由硅制成，填充沟槽的步骤包括使用硅源气体进行等离子体CVD法的步骤。 通过使用等离子体的各向异性特征，外延层选择性地沉积在沟槽的底部。 因此，沟槽被无空隙的外延层填充。
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9.发明申请公开(公告)号：US20070072398A1
公开(公告)日：2007-03-29
申请号：US11528678
申请日：2006-09-28
IPC分类号： H01L21/20
CPC分类号： H01L29/7813 , H01L21/02381 , H01L21/0243 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L29/045 , H01L29/0634 , H01L29/66734 , H01L29/7811
摘要： A method for manufacturing a semiconductor device includes steps of: forming a trench on a main surface of a silicon substrate; forming a first epitaxial film on the main surface and in the trench; and forming a second epitaxial film on the first epitaxial film. The step of forming the first epitaxial film has a first process condition with a first growth rate of the first epitaxial film. The step of forming the second epitaxial film has a second process condition with a second growth rate of the second epitaxial film. The second growth rate is larger than the first growth rate.
摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在硅衬底的主表面上形成沟槽; 在主表面和沟槽中形成第一外延膜; 以及在所述第一外延膜上形成第二外延膜。 形成第一外延膜的步骤具有第一外延膜的第一生长速率的第一工艺条件。 形成第二外延膜的步骤具有第二外延膜的第二生长速率的第二工艺条件。 第二增长率大于第一增长率。
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公开(公告)号：US06525375B1
公开(公告)日：2003-02-25
申请号：US09688154
申请日：2000-10-16
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/04 , H01L29/045 , H01L29/0696 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/4238 , H01L29/66348 , H01L29/66378 , H01L29/66659 , H01L29/66704 , H01L29/66734 , H01L29/66787 , H01L29/7393 , H01L29/7397 , H01L29/749 , H01L29/78 , H01L29/7803 , H01L29/7809 , H01L29/7816 , H01L29/7817 , H01L29/7824 , H01L29/7825 , H01L29/7828 , H01L29/7835
摘要： In a semiconductor device, a p-type base region is provided in an n−-type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n+-type source region extends in the p-type base region from the principal surface in the perpendicular direction, and an n+-type drain region extends in the substrate separately from the p-type base region with a drift region interposed therebetween. A trench is formed to penetrate the p-type base region from the n+-type source region in a direction parallel to the principal surface. A gate electrode is formed in the trench through a gate insulating film. Accordingly, a channel region can be formed with a channel width in a depth direction of the trench when a voltage is applied to the gate electrode.
摘要翻译： 在半导体器件中，p型基极区域设置在n型衬底中，以从垂直于主表面的方向从衬底的主表面延伸。 n +型源极区域在垂直方向上从主表面延伸到p型基极区域中，并且n +型漏极区域在p型基极区域中与P型基极区域分开延伸，并且其间插入漂移区域。 形成沟槽，以在平行于主表面的方向上从n +型源极区域穿透p型基极区域。 栅电极通过栅极绝缘膜形成在沟槽中。 因此，当向栅电极施加电压时，可以在沟槽的深度方向上形成沟道区域。
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