公开(公告)号：US20080182387A1

公开(公告)日：2008-07-31

申请号：US11701561

申请日：2007-01-31

申请人： Tao Feng ,  Ming Sun ,  Yueh-Se Ho ,  Kai Liu

发明人： Tao Feng ,  Ming Sun ,  Yueh-Se Ho ,  Kai Liu

IPC分类号： H01L21/00

CPC分类号： H01L21/67132 ,  H01L21/288 ,  H01L21/6836 ,  H01L24/02 ,  H01L24/11 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014

摘要： A method of fabricating a semiconductor device employing electroless plating including wafer backside protection during wet processing is disclosed. The method includes the steps of laminating a wafer back side and a frame with a protective tape, applying a protective coating to a peripheral portion of the wafer and an adjoining exposed area of the protective tape, the protective coating, protective tape, and wafer forming a protected wafer assembly, curing the frame-supported protective coating, cutting the protected wafer assembly from the protective tape surrounding the protective coating, wet processing the protected wafer assembly, laminating the protected wafer assembly with a second tape, dicing the wafer, and picking up the die from the protective tape.

摘要翻译： 公开了一种在湿法处理中制造采用化学镀的半导体器件的方法，包括晶片背面保护。 该方法包括以下步骤：将晶片背面和框架与保护带层压，将保护涂层施加到晶片的周边部分以及相邻的保护带的暴露区域，保护涂层，保护带和晶片成形 保护的晶片组件，固化框架支撑的保护涂层，将保护的晶片组件从围绕保护涂层的保护带切割，湿处理受保护的晶片组件，用第二带层压受保护的晶片组件，切割晶片，以及拾取 从保护胶带上取下模具。

公开(公告)号：US07811904B2

公开(公告)日：2010-10-12

申请号：US11701561

申请日：2007-01-31

申请人： Tao Feng ,  Ming Sun ,  Yueh-Se Ho ,  Kai Liu

发明人： Tao Feng ,  Ming Sun ,  Yueh-Se Ho ,  Kai Liu

IPC分类号： H01L21/00

CPC分类号： H01L21/67132 ,  H01L21/288 ,  H01L21/6836 ,  H01L24/02 ,  H01L24/11 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014

摘要： A method of fabricating a semiconductor device employing electroless plating including wafer backside protection during wet processing is disclosed. The method includes the steps of laminating a wafer back side and a frame with a protective tape, applying a protective coating to a peripheral portion of the wafer and an adjoining exposed area of the protective tape, the protective coating, protective tape, and wafer forming a protected wafer assembly, curing the frame-supported protective coating, cutting the protected wafer assembly from the protective tape surrounding the protective coating, wet processing the protected wafer assembly, laminating the protected wafer assembly with a second tape, dicing the wafer, and picking up the die from the protective tape.

摘要翻译： 公开了一种在湿法处理中制造采用化学镀的半导体器件的方法，包括晶片背面保护。 该方法包括以下步骤：将晶片背面和框架与保护带层压，将保护涂层施加到晶片的周边部分以及相邻的保护带的暴露区域，保护涂层，保护带和晶片成形 保护的晶片组件，固化框架支撑的保护涂层，将保护的晶片组件从围绕保护涂层的保护带切割，湿处理受保护的晶片组件，用第二带层压受保护的晶片组件，切割晶片，以及拾取 从保护胶带上取下模具。

公开(公告)号：US20150102425A1

公开(公告)日：2015-04-16

申请号：US14052711

申请日：2013-10-12

申请人： Ming Sun ,  Kai Liu ,  Xiao Tian Zhang ,  Yueh Se Ho ,  Leeshawn Luo

发明人： Ming Sun ,  Kai Liu ,  Xiao Tian Zhang ,  Yueh Se Ho ,  Leeshawn Luo

IPC分类号： H01L23/495 ,  H01L29/78 ,  H01L29/66 ,  H01L23/00

CPC分类号： H01L23/49562 ,  H01L23/492 ,  H01L23/4928 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/97 ,  H01L29/66477 ,  H01L29/78 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/83205 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83895 ,  H01L2224/97 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/014

摘要： A power device package for containing, protecting and providing electrical contacts for a power transistor includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy.

摘要翻译： 用于容纳，保护和提供用于功率晶体管的电触头的功率器件封装包括用于直接不连接到功率晶体管的顶部和底部引线框架。 功率晶体管作为具有源极接触的倒装芯片附接到底部引线框架，并且栅极接触件直接地不连接到底部引线框架上。 功率晶体管具有附接到顶部引线框架的底部漏极接触。 顶部引线框架还包括用于提供与底部引线框架基本上在同一侧上的底部漏极电极的延伸部分。 在优选实施例中，功率器件封装还包括通过施加超声波能量的源极，栅极或漏极以及顶部或底部引线框架的器件金属之间的接合层。

公开(公告)号：US08564049B2

公开(公告)日：2013-10-22

申请号：US11894240

申请日：2008-03-31

申请人： Ming Sun ,  Kai Liu ,  Xiao Tian Zhang ,  Yueh Se Ho ,  Leeshawn Luo

发明人： Ming Sun ,  Kai Liu ,  Xiao Tian Zhang ,  Yueh Se Ho ,  Leeshawn Luo

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L24/33 ,  H01L29/045 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7811 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

摘要： This invention discloses a power device package for containing, protecting and providing electrical contacts for a power transistor. The power device package includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy. In another embodiment, a layer of conductive epoxy or adhesive, a solder paste, a carbon paste, or other types of attachment agents for direct no-bumping attaching the power transistor to one of the top and bottom lead frames.

摘要翻译： 本发明公开了一种功率器件封装，用于容纳，保护和提供功率晶体管的电触头。 功率器件封装包括用于直接不连接到功率晶体管的顶部和底部引线框架。 功率晶体管作为具有源极接触的倒装芯片附接到底部引线框架，并且栅极接触件直接地不连接到底部引线框架上。 功率晶体管具有附接到顶部引线框架的底部漏极接触。 顶部引线框架还包括用于提供与底部引线框架基本上在同一侧上的底部漏极电极的延伸部分。 在优选实施例中，功率器件封装还包括通过施加超声波能量的源极，栅极或漏极以及顶部或底部引线框架的器件金属之间的接合层。 在另一个实施方案中，导电环氧树脂或粘合剂层，焊膏，碳糊或其它类型的附着剂用于将功率晶体管附接到顶引线框架和底引线框架之一的直接无凸起。

公开(公告)号：US08513784B2

公开(公告)日：2013-08-20

申请号：US12726892

申请日：2010-03-18

申请人： Jun Lu ,  Ming Sun ,  Yueh-Se Ho ,  Kai Liu ,  Lei Shi

发明人： Jun Lu ,  Ming Sun ,  Yueh-Se Ho ,  Kai Liu ,  Lei Shi

IPC分类号： H01L23/495 ,  H01L23/48

CPC分类号： H01L21/56 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/83 ,  H01L24/84 ,  H01L24/97 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40249 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/73263 ,  H01L2224/83 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/8485 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/84 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2924/00014

摘要： The present invention features a lead-frame package, having a first, second, third and fourth electrically conductive structures with a pair of semiconductor dies disposed therebetween defining a stacked structure. The first and second structures are spaced-apart from and in superimposition with the first structure. A semiconductor die is disposed between the first and second structures. The semiconductor die has contacts electrically connected to the first and second structures. A part of the third structure lies in a common plane with a portion of the second structure. The third structure is coupled to the semiconductor die. An additional semiconductor die is attached to one of the first and second structures. The fourth structure is in electrical contact with the additional semiconductor die. A molding compound is disposed to encapsulate a portion of said package with a sub-portion of the molding compound being disposed in the volume.

摘要翻译： 本发明的特征在于具有第一，第二，第三和第四导电结构的引线框架封装，其中设置在其间的一对半导体管芯限定堆叠结构。 第一和第二结构与第一结构隔开并与第一结构重叠。 半导体管芯设置在第一和第二结构之间。 半导体管芯具有电连接到第一和第二结构的触点。 第三结构的一部分位于具有第二结构的一部分的共同平面中。 第三结构耦合到半导体管芯。 附加的半导体管芯附接到第一和第二结构中的一个。 第四结构与附加的半导体管芯电接触。 设置模塑料以封装所述包装的一部分，其中模制化合物的一部分设置在体积中。

公开(公告)号：US20080211070A1

公开(公告)日：2008-09-04

申请号：US11894240

申请日：2008-03-31

申请人： Ming Sun ,  Kai Liu ,  Xiao Tian Zhang ,  Yueh Se Ho ,  Leeshawn Luo

发明人： Ming Sun ,  Kai Liu ,  Xiao Tian Zhang ,  Yueh Se Ho ,  Leeshawn Luo

IPC分类号： H01L23/495

CPC分类号： H01L29/7813 ,  H01L24/33 ,  H01L29/045 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7811 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

摘要： This invention discloses a power device package for containing, protecting and providing electrical contacts for a power transistor. The power device package includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy. In another embodiment, a layer of conductive epoxy or adhesive, a solder paste, a carbon paste, or other types of attachment agents for direct no-bumping attaching the power transistor to one of the top and bottom lead frames.

摘要翻译： 本发明公开了一种功率器件封装，用于容纳，保护和提供功率晶体管的电触头。 功率器件封装包括用于直接不连接到功率晶体管的顶部和底部引线框架。 功率晶体管作为具有源极接触的倒装芯片附接到底部引线框架，并且栅极接触件直接地不连接到底部引线框架上。 功率晶体管具有附接到顶部引线框架的底部漏极接触。 顶部引线框架还包括用于提供与底部引线框架基本上在同一侧上的底部漏极电极的延伸部分。 在优选实施例中，功率器件封装还包括通过施加超声波能量的源极，栅极或漏极以及顶部或底部引线框架的器件金属之间的接合层。 在另一个实施方案中，导电环氧树脂或粘合剂层，焊膏，碳糊或其它类型的附着剂用于将功率晶体管附接到顶引线框架和底引线框架之一的直接无凸起。

公开(公告)号：US09337132B2

公开(公告)日：2016-05-10

申请号：US14052711

申请日：2013-10-12

申请人： Ming Sun ,  Kai Liu ,  Xiaotian Zhang ,  Yueh Se Ho ,  Leeshawn Luo

发明人： Ming Sun ,  Kai Liu ,  Xiaotian Zhang ,  Yueh Se Ho ,  Leeshawn Luo

IPC分类号： H01L23/495 ,  H01L29/78 ,  H01L23/00 ,  H01L29/66 ,  H01L23/492

CPC分类号： H01L23/49562 ,  H01L23/492 ,  H01L23/4928 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/97 ,  H01L29/66477 ,  H01L29/78 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/83205 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83895 ,  H01L2224/97 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/014

摘要： A power device package for containing, protecting and providing electrical contacts for a power transistor includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy.

摘要翻译： 用于容纳，保护和提供用于功率晶体管的电触头的功率器件封装包括用于直接不连接到功率晶体管的顶部和底部引线框架。 功率晶体管作为具有源极接触的倒装芯片附接到底部引线框架，并且栅极接触件直接地不连接到底部引线框架上。 功率晶体管具有附接到顶部引线框架的底部漏极接触。 顶部引线框架还包括用于提供与底部引线框架基本上在同一侧上的底部漏极电极的延伸部分。 在优选实施例中，功率器件封装还包括通过施加超声波能量的源极，栅极或漏极以及顶部或底部引线框架的器件金属之间的接合层。

公开(公告)号：US20110227205A1

公开(公告)日：2011-09-22

申请号：US12726892

申请日：2010-03-18

申请人： Jun Lu ,  Ming Sun ,  Yueh-Se Ho ,  Kai Liu ,  Lei Shi

发明人： Jun Lu ,  Ming Sun ,  Yueh-Se Ho ,  Kai Liu ,  Lei Shi

IPC分类号： H01L23/52 ,  H01L21/60 ,  H01L23/538

CPC分类号： H01L21/56 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/83 ,  H01L24/84 ,  H01L24/97 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40249 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/73263 ,  H01L2224/83 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/8485 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/84 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2924/00014

摘要： The present invention features a lead-frame package, having a first, second, third and fourth electrically conductive structures with a pair of semiconductor dies disposed therebetween defining a stacked structure. The first and second structures are spaced-apart from and in superimposition with the first structure. A semiconductor die is disposed between the first and second structures. The semiconductor die has contacts electrically connected to the first and second structures. A part of the third structure lies in a common plane with a portion of the second structure. The third structure is coupled to the semiconductor die. An additional semiconductor die is attached to one of the first and second structures. The fourth structure is in electrical contact with the additional semiconductor die. A molding compound is disposed to encapsulate a portion of said package with a sub-portion of the molding compound being disposed in the volume.

摘要翻译： 本发明的特征在于具有第一，第二，第三和第四导电结构的引线框架封装，其中设置在其间的一对半导体管芯限定堆叠结构。 第一和第二结构与第一结构隔开并与第一结构重叠。 半导体管芯设置在第一和第二结构之间。 半导体管芯具有电连接到第一和第二结构的触点。 第三结构的一部分位于具有第二结构的一部分的共同平面中。 第三结构耦合到半导体管芯。 附加的半导体管芯附接到第一和第二结构中的一个。 第四结构与附加的半导体管芯电接触。 设置模塑料以封装所述包装的一部分，其中模制化合物的一部分设置在体积中。

公开(公告)号：US08581376B2

公开(公告)日：2013-11-12

申请号：US12819111

申请日：2010-06-18

申请人： Hamza Yilmaz ,  Xiaotian Zhang ,  Yan Xun Xue ,  Anup Bhalla ,  Jun Lu ,  Kai Liu ,  Yueh-Se Ho ,  John Amato

发明人： Hamza Yilmaz ,  Xiaotian Zhang ,  Yan Xun Xue ,  Anup Bhalla ,  Jun Lu ,  Kai Liu ,  Yueh-Se Ho ,  John Amato

IPC分类号： H01L21/44 ,  H01L21/31

CPC分类号： H01L23/49541 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/81 ,  H01L24/84 ,  H01L2224/27013 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45014 ,  H01L2224/48247 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01067 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

摘要： The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication.

摘要翻译： 本发明涉及具有插入金属夹结构的半导体管芯堆叠的引线框架。 水平投影从夹子结构延伸，以确保夹子结构在制造过程中保持水平。

公开(公告)号：US20110227207A1

公开(公告)日：2011-09-22

申请号：US12819111

申请日：2010-06-18

申请人： Hamza Yilmaz ,  Xiaotian Zhang ,  Yan Xun Xue ,  Anup Bhalla ,  Jun Lu ,  Kai Liu ,  Yueh-Se Ho ,  John Amato

发明人： Hamza Yilmaz ,  Xiaotian Zhang ,  Yan Xun Xue ,  Anup Bhalla ,  Jun Lu ,  Kai Liu ,  Yueh-Se Ho ,  John Amato

IPC分类号： H01L23/52 ,  H01L23/495 ,  H01L21/00

CPC分类号： H01L23/49541 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/81 ,  H01L24/84 ,  H01L2224/27013 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45014 ,  H01L2224/48247 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01067 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

摘要： The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication.

摘要翻译： 本发明涉及具有插入金属夹结构的半导体管芯堆叠的引线框架。 水平投影从夹子结构延伸，以确保夹子结构在制造过程中保持水平。