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28 条记录 (耗时 0.019 秒)

    Semiconductor device
    1.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20080042193A1

    公开(公告)日：2008-02-21

    申请号：US11896800

    申请日：2007-09-06

    申请人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

    发明人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11521 ,  B82Y10/00 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/06 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7887

    摘要： For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.

    摘要翻译： 为了通过电池级提供具有提高可靠性的便宜的半导体存储器件，以代替通过诸如ECC的电存储器单元中的缺陷脱离，并且还用于提供能够在垂直方向上按比例缩小的单元结构，同时保持 在需要高速读出操作的半导体存储器件中的可靠性，电荷存储区域由大量半导体电荷存储小区域制成的粒子构成，各自独立，从而通过 细胞水平。

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20110169070A1

    公开(公告)日：2011-07-14

    申请号：US13072211

    申请日：2011-03-25

    申请人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

    发明人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

    IPC分类号： H01L27/088

    CPC分类号： H01L27/11521 ,  B82Y10/00 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/06 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7887

    摘要： For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.

    摘要翻译： 为了通过电池级提供具有提高可靠性的便宜的半导体存储器件，以代替通过诸如ECC的电存储器单元中的缺陷脱离，并且还用于提供能够在垂直方向上按比例缩小的单元结构，同时保持 在需要高速读出操作的半导体存储器件中的可靠性，电荷存储区域由大量半导体电荷存储小区域制成的粒子构成，各自独立，从而通过 细胞水平。

    Semiconductor memory device and method for producing the same
    6.
    发明授权
    Semiconductor memory device and method for producing the same 失效
    半导体存储器件及其制造方法

    公开(公告)号：US07622766B2

    公开(公告)日：2009-11-24

    申请号：US11808228

    申请日：2007-06-07

    申请人： Tomoyuki Ishii ,  Taro Osabe ,  Hideaki Kurata ,  Takeshi Sakata

    发明人： Tomoyuki Ishii ,  Taro Osabe ,  Hideaki Kurata ,  Takeshi Sakata

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11568 ,  B82Y10/00 ,  G11C11/5621 ,  G11C11/5671 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0475 ,  G11C16/0491 ,  G11C2216/06 ,  H01L27/115 ,  H01L27/11521

    摘要： Disclosed is a non-volatile semiconductor memory device that uses a inversion layer provided on a semiconductor substrate as a data line. The memory device can reduce variation of characteristics among memory cells and can reduce bit cost. A plurality of assist gates are formed in the upper part of a p-type well through a gate oxide film. In the upper part of an interlayer insulator that covers those assist gates are formed word lines that are used as control electrodes. The width of those word lines is, for example, 0.1 μm, and each word line is separated from its adjacent word lines by a side wall spacer that is a silicon oxide film having a thickness of about 20 nm.

    摘要翻译： 公开了使用设置在半导体衬底上的反转层作为数据线的非易失性半导体存储器件。 存储器件可以减少存储器单元之间的特性变化并且可以降低位成本。 多个辅助栅极通过栅极氧化膜形成在p型阱的上部。 在覆盖这些辅助栅极的层间绝缘体的上部形成用作控制电极的字线。 这些字线的宽度例如为0.1μm，并且每个字线通过作为厚度为约20nm的氧化硅膜的侧壁间隔物与其相邻字线分开。

    Semiconductor memory element, semiconductor device and control method thereof
    7.
    发明授权
    Semiconductor memory element, semiconductor device and control method thereof 有权
    半导体存储元件，半导体器件及其控制方法

    公开(公告)号：US06815763B2

    公开(公告)日：2004-11-09

    申请号：US10082205

    申请日：2002-02-26

    申请人： Taro Osabe ,  Tomoyuki Ishii

    发明人： Taro Osabe ,  Tomoyuki Ishii

    IPC分类号： H01L29792

    CPC分类号： H01L29/42332 ,  G11C16/0408 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/7885

    摘要： In a semiconductor flash memory required to have high reliability, injection and extraction of electrons must be performed through an oxide film obtained by directly oxidizing a silicon substrate. Accordingly, the voltage to be used is a large voltage ranging from positive to negative one. In contrast, by storing charges in a plurality of dispersed regions, high reliability is achieved. Based on the high reliability, transfer of electrons is permitted through not only the oxide film obtained by directly thermally oxidizing a high reliability silicon substrate but also another oxide film deposited by CVD, or the like. In consequence, a device is controlled by electric potentials of the same polarity upon writing of data and upon erasing of data.

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08278700B2

    公开(公告)日：2012-10-02

    申请号：US13072211

    申请日：2011-03-25

    申请人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

    发明人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11521 ,  B82Y10/00 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/06 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7887

    摘要： For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.

    摘要翻译： 为了通过电池级提供具有提高可靠性的便宜的半导体存储器件，以代替通过诸如ECC的电存储器单元中的缺陷脱离，并且还用于提供能够在垂直方向上按比例缩小的单元结构，同时保持 在需要高速读出操作的半导体存储器件中的可靠性，电荷存储区域由大量半导体电荷存储小区域制成的粒子构成，各自独立，从而通过 细胞水平。

    Semiconductor device
    9.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07939879B2

    公开(公告)日：2011-05-10

    申请号：US11896800

    申请日：2007-09-06

    申请人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

    发明人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11521 ,  B82Y10/00 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/06 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7887

    摘要： For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.

    摘要翻译： 为了通过电池级提供具有提高可靠性的便宜的半导体存储器件，以代替通过诸如ECC的电存储器单元中的缺陷脱离，并且还用于提供能够在垂直方向上按比例缩小的单元结构，同时保持 在需要高速读出操作的半导体存储器件中的可靠性，电荷存储区域由大量半导体电荷存储小区域制成的粒子构成，各自独立，从而通过 细胞水平。

    Non-volatile semiconductor memory
    10.
    发明授权
    Non-volatile semiconductor memory 有权
    非易失性半导体存储器

    公开(公告)号：US07045854B2

    公开(公告)日：2006-05-16

    申请号：US10689101

    申请日：2003-10-21

    申请人： Taro Osabe ,  Tomoyuki Ishii ,  Takashi Kobayashi

    发明人： Taro Osabe ,  Tomoyuki Ishii ,  Takashi Kobayashi

    IPC分类号： H01L29/788

    CPC分类号： H01L21/28273 ,  B82Y10/00 ,  G11C16/0475 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923

    摘要： An object of the present invention is to provide a semiconductor memory device suitable for larger-capacity storage because of its ability to store 3 or more bits in one element and capable of a high-speed and high-efficiency write operation due to a reduced leakage current during the write operation and provide a fabrication method therefor. According to the present invention, each of elements has a source region, a drain region, a control gate, two charge storage regions, and one or more assist gates. During a write operation, source side injection writing is performed with respect to a write target element by using the assist gates, while adjacent elements are isolated by field isolation using the assist gates.

    摘要翻译： 本发明的目的是提供一种适用于大容量存储的半导体存储器件，因为它能够在一个元件中存储3个或更多个位并能够由于泄漏减少而进行高速和高效率的写入操作 在写操作期间提供电流并提供其制造方法。 根据本发明，每个元件具有源极区，漏极区，控制栅极，两个电荷存储区域以及一个或多个辅助栅极。 在写入操作期间，通过使用辅助栅极相对于写入目标元件执行源侧注入写入，而通过使用辅助栅极的场隔离来隔离相邻元件。