公开(公告)号：US06057187A

公开(公告)日：2000-05-02

申请号：US164354

申请日：1998-10-01

Applicant: Tean-Sen Jen ,  Shiou-Yu Wang ,  Jia-Shyong Cheng

Inventor： Tean-Sen Jen ,  Shiou-Yu Wang ,  Jia-Shyong Cheng

IPC: H01L27/108 ,  H10L21/8242

CPC classification number: H01L27/10805 ,  H01L27/10808 ,  Y10S257/904 ,  Y10S257/906

Abstract: The present invention discloses a DRAM structure with multiple memory cells sharing the same bit-line contact. The DRAM structure of the present invention comprises: a substrate; an active region formed on the substrate, with a center region and a plurality of protrusion regions connecting to the two sides of the center region; a plurality of word-lines, disconnected from each other, each crossing the corresponding protrusion region; a plurality of channel regions, formed where the protrusion region overlaps with the word-lines; a plurality of source regions, formed at the outer areas of the channel regions; a sharing drain region, formed at the center region of the active region; a bit-line contact, formed on surface of the sharing drain region; a bit-line, crossing the center region and electrically connected to the sharing drain region via the bit-line contact; a plurality of capacitors, electrically connected to the source regions; and a plurality of metal lines, electrically connected to the corresponding word-lines.

Abstract translation: 本发明公开了具有共享相同位线接触的多个存储单元的DRAM结构。 本发明的DRAM结构包括：基板; 形成在所述基板上的有源区域，具有连接到所述中心区域的两侧的中心区域和多个突出区域; 多个字线彼此断开，每个字线与相应的突出区域交叉; 多个通道区域，形成在突起区域与字线重叠的位置上; 多个源区，形成在沟道区的外部区域; 形成在有源区的中心区域的共用漏极区; 形成在共享漏极区域的表面上的位线接触; 位线，穿过中心区域并且经由位线接触电连接到共享漏极区域; 多个电容器，电连接到源极区域; 和多个金属线，电连接到相应的字线。

公开(公告)号：US5989952A

公开(公告)日：1999-11-23

申请号：US934617

申请日：1997-09-22

Applicant: Tean-Sen Jen ,  Shiou-Yu Wang ,  Jia-Shyong Cheng ,  Chi-Hui Lin

Inventor： Tean-Sen Jen ,  Shiou-Yu Wang ,  Jia-Shyong Cheng ,  Chi-Hui Lin

IPC: C12Q1/48 ,  H01L21/02 ,  H01L21/8242 ,  H01L12/8242

CPC classification number: H01L28/92 ,  C12Q1/48 ,  H01L27/10852

Abstract: A method for fabricating a DRAM cell having a crown-type capacitor over a semiconductor substrate is disclosed. The method includes steps of: (a) forming a transistor over the semiconductor substrate; (b) forming an insulating layer over the transistor; (c) selectively etching the insulating layer to form a contact opening; (d) forming a first conducting layer over the insulating layer and filling into the contact opening; (e) forming an etching stop layer and a mask layer over the first conducting layer; (f) pattering the mask layer to form a plurality of openings; (g) forming a dielectric spacer on the sidewall of the mask layer, and removing exposed portions of the etching stop layer; (h) anisotropically etching the mask layer and the first conducting layer by using the dielectric spacer as a mask, to expose, respectively, the etching stop layer and the insulating layer; (i) removing uncovered etching stop layer to expose the first conducting layer; (j) anisotropically etching the first conducting layer to a predetermined depth by using the dielectric spacer as a mask, thereby forming a crown-type storage electrode; (k) removing the dielectric spacer and the etching stop layer; (l) forming a dielectric layer over exposed portions of the storage electrode; and (m) forming a second conducting layer as an opposite electrode over the dielectric layer.

Abstract translation: 公开了一种在半导体衬底上制造具有冠型电容器的DRAM单元的方法。 该方法包括以下步骤：（a）在半导体衬底上形成晶体管; （b）在所述晶体管上形成绝缘层; （c）选择性地蚀刻绝缘层以形成接触开口; （d）在所述绝缘层上形成第一导电层并填充到所述接触开口中; （e）在所述第一导电层上形成蚀刻停止层和掩​​模层; （f）图案掩模层以形成多个开口; （g）在掩模层的侧壁上形成电介质间隔物，去除蚀刻停止层的暴露部分; （h）通过使用电介质间隔物作为掩模，各向异性地蚀刻掩模层和第一导电层，分别暴露蚀刻停止层和绝缘层; （i）去除未覆盖的蚀刻停止层以暴露第一导电层; （j）通过使用电介质间隔物作为掩模，将第一导电层各向异性蚀刻到预定深度，由此形成冠型存储电极; （k）去除电介质间隔物和蚀刻停止层; （l）在所述存储电极的暴露部分上形成介电层; 和（m）在所述电介质层上形成作为相对电极的第二导电层。

公开(公告)号：US5955757A

公开(公告)日：1999-09-21

申请号：US54547

申请日：1998-04-03

Applicant: Tean-Sen Jen ,  Shiou-Yu Wang ,  Jia-Shyong Cheng

Inventor： Tean-Sen Jen ,  Shiou-Yu Wang ,  Jia-Shyong Cheng

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/10808 ,  Y10S257/904 ,  Y10S257/906

Abstract: The present invention discloses a DRAM structure with multiple memory cells sharing the same bit-line contact. The DRAM structure of the present invention comprises: a substrate; an active region formed on the substrate, with a center region and a plurality of protrusion regions connecting to the two sides of the center region; a plurality of word-lines, disconnected from each other, each crossing the corresponding protrusion region; a plurality of channel regions, formed where the protrusion region overlaps with the word-lines; a plurality of source regions, formed at the outer areas of the channel regions; a sharing drain region, formed at the center region of the active region; a bit-line contact, formed on surface of the sharing drain region; a bit-line, crossing the center region and electrically connected to the sharing drain region via the bit-line contact; a plurality of capacitors, electrically connected to the source regions; and a plurality of metal lines, electrically connected to the corresponding word-lines.

Abstract translation: 本发明公开了具有共享相同位线接触的多个存储单元的DRAM结构。 本发明的DRAM结构包括：基板; 形成在所述基板上的有源区域，具有连接到所述中心区域的两侧的中心区域和多个突出区域; 多个字线彼此断开，每个字线与相应的突出区域交叉; 多个通道区域，形成在突起区域与字线重叠的位置上; 多个源区，形成在沟道区的外部区域; 形成在有源区的中心区域的共用漏极区; 形成在共享漏极区域的表面上的位线接触; 位线，穿过中心区域并且经由位线接触电连接到共享漏极区域; 多个电容器，电连接到源极区域; 和多个金属线，电连接到相应的字线。

公开(公告)号：US06372560B1

公开(公告)日：2002-04-16

申请号：US09540593

申请日：2000-03-31

Applicant: Tean-Sen Jen ,  Jia-Shyong Cheng

Inventor： Tean-Sen Jen ,  Jia-Shyong Cheng

IPC: H01L2100

CPC classification number: H01L27/1288 ,  G02F1/1368 ,  G02F2001/136231 ,  H01L27/1214

Abstract: A simplified process for forming a thin film transistor matrix for a liquid crystal display is disclosed. By forming and patterning a conductive layer overlying a TFT unit, a data line, a first connection line between the TFT unit and the data line, and a second connection line between the TFT unit and a pixel electrode can be simultaneously formed in the forming and patterning step. Furthermore, after a passivation layer is applied to protect the TFT matrix, an isolation window area, a contact hole and a TAB window can be created in a single patterning step. Therefore, masking steps can be reduced so as to simplify the process. On the other hand, owing to the first connection line for connecting the TFT unit and the scan line is of the same material as the scan line, the resistivity of the connection line is inherently low. Therefore, a TFTLCD of a large area can be made according to this process.

Abstract translation: 公开了用于形成用于液晶显示器的薄膜晶体管矩阵的简化过程。 通过形成和图案化覆盖TFT单元的导电层，可以在成形和/或形成中同时形成数据线，TFT单元和数据线之间的第一连接线以及TFT单元和像素电极之间的第二连接线 图案化步骤。 此外，在施加钝化层以保护TFT矩阵之后，可以在单个图案化步骤中创建隔离窗口区域，接触孔和TAB窗口。 因此，可以减少掩蔽步骤，以简化处理。 另一方面，由于用于连接TFT单元和扫描线的第一连接线具有与扫描线相同的材料，所以连接线的电阻率固有地较低。 因此，可以根据该过程制造大面积的TFTLCD。

公开(公告)号：US06448117B1

公开(公告)日：2002-09-10

申请号：US09656093

申请日：2000-09-06

Applicant: Tean-Sen Jen ,  Jia-Shyong Cheng

Inventor： Tean-Sen Jen ,  Jia-Shyong Cheng

IPC: H01L2128

CPC classification number: H01L29/66765 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/78633

Abstract: A simplified tri-layer process for forming a thin film transistor matrix for a liquid crystal display is disclosed. By forming a pixel electrode layer before a gate metal layer, a remaining portion of the gate metal layer surrounding the pixel electrode can function as a black matrix after properly patterning and etching the gate metal layer. The in-situ black matrix exempts from an additional step of providing a black matrix and solves the problem in alignment.

Abstract translation: 公开了用于形成用于液晶显示器的薄膜晶体管矩阵的简化三层工艺。 通过在栅极金属层之前形成像素电极层，围绕像素电极的栅极金属层的剩余部分在适当地构图和蚀刻栅极金属层之后可以用作黑色矩阵。 原位黑矩阵免除了提供黑矩阵的额外步骤，并解决了对准中的问题。

公开(公告)号：US06436740B1

公开(公告)日：2002-08-20

申请号：US09615919

申请日：2000-07-13

Applicant: Tean-Sen Jen ,  Jia-Shyong Cheng

Inventor： Tean-Sen Jen ,  Jia-Shyong Cheng

IPC: H01L2100

CPC classification number: H01L29/66765

Abstract: A simplified tri-layer process for forming a thin film transistor matrix for a liquid crystal display is disclosed. By using a backside exposure technique, the masking step for patterning an etch stopper layer can be omitted. After forming an active region including a gate electrode and a scan line on the front side of a substrate, and sequentially applying an etch stopper layer and a photoresist layer over the resulting structure, the backside exposure is performed by exposing from the back side of the substrate. A portion of photoresist is shielded by the active region from exposure so that an etch stopper structure having a shape similar to the shape of the active region is formed without any photo-masking and lithographic procedure. Therefore, the above self-aligned effect allows one masking step to be reduced so as to simplify the process.

公开(公告)号：US5966610A

公开(公告)日：1999-10-12

申请号：US2675

申请日：1998-01-05

Applicant: Shiou-Yu Wang ,  Tean-Sen Jen ,  Jia-Shyong Cheng

Inventor： Shiou-Yu Wang ,  Tean-Sen Jen ,  Jia-Shyong Cheng

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC classification number: H01L28/92 ,  H01L28/91 ,  H01L27/10814 ,  H01L27/10852

Abstract: A method of fabricating a capacitor plate constitutes first providing a substrate. Then, first insulating layer is formed over the substrate. Sequentially, a buffering layer and a second insulating layer, both of which constitute a stacked structure, are formed over the first insulating layer. Next, the stacked structure is patterned into an opening thereby exposing a portion of the first insulating layer therethrough. Subsequently, conducting spacers are formed on the sidewalls of the opening. The second insulating layer is thereafter removed, and simultaneously a portion of the first insulating layer not covered by the buffering layer and the conducting spacers are removed to form a contact window, thereby exposing a portion of the substrate therethrough. Then, a conducting layer is conformably deposited over the substrate, and thereafter etched away until a portion of the buffering layer is exposed. Finally, the exposed buffering layer is removed. The remaining conducting layer and the conducting spacers constitute the capacitor's bottom electrode plate.

Abstract translation: 构成电容器板的方法首先构成基板。 然后，在基板上形成第一绝缘层。 顺序地，在第一绝缘层上形成缓冲层和构成堆叠结构的第二绝缘层。 接下来，将堆叠结构图案化成开口，从而使第一绝缘层的一部分暴露于其中。 随后，在开口的侧壁上形成导电间隔物。 此后除去第二绝缘层，同时将不被缓冲层和导电间隔物覆盖的第一绝缘层的一部分移除以形成接触窗，从而使基板的一部分暴露。 然后，将导电层顺应地沉积在衬底上，然后蚀刻掉直到缓冲层的一部分露出。 最后，暴露的缓冲层被去除。 剩余的导电层和导电间隔物构成电容器的底部电极板。

公开(公告)号：US5960295A

公开(公告)日：1999-09-28

申请号：US009160

申请日：1998-01-20

Applicant: Tean-Sen Jen ,  Shiou-Yu Wang ,  Jia-Shyong Cheng

Inventor： Tean-Sen Jen ,  Shiou-Yu Wang ,  Jia-Shyong Cheng

IPC: H01L21/02 ,  H01L21/20

CPC classification number: H01L28/92

Abstract: The present invention provides a method for fabricating a storage plate of a semiconductor capacitor. A conductive layer is first formed on a semiconductor substrate. A glue layer is formed on the conductive layer. A plurality of micro masking-balls are then spread onto the surface of the glue layer. Using these micro masking-balls as masks, the glue layer is etched to expose a portion surface of the conductive layer. Using the remaining glue layer as a mask, the conductive layer is etched to form a bristle-shaped conductive layer. After that, the glue layer and micro masking-balls are removed, thereby allowing the remaining bristle-shaped conductive layer to form a storage plate of a semiconductor capacitor.

Abstract translation: 本发明提供一种制造半导体电容器的存储板的方法。 首先在半导体衬底上形成导电层。 在导电层上形成胶层。 然后将多个微掩模球展开到胶层的表面上。 使用这些微掩模球作为掩模，蚀刻胶层以暴露导电层的部分表面。 使用剩余的胶层作为掩模，蚀刻导电层以形成刷毛状导电层。 之后，去除胶层和微掩模球，由此使残留的刷毛状导电层形成半导体电容器的存储板。

公开(公告)号：US06721026B2

公开(公告)日：2004-04-13

申请号：US09846462

申请日：2001-05-01

Applicant: Jia-Shyong Cheng ,  Tean-Sen Jen

Inventor： Jia-Shyong Cheng ,  Tean-Sen Jen

IPC: G02F11333

CPC classification number: G02F1/134363

Abstract: A process for forming an in-plane switching mode liquid crystal display (IPS-LCD), which defines pixel portions of the common and data electrodes by the same photo-masking and lithography procedure, is disclosed. Accordingly, the misalignment can be avoid. An in-plane switching mode liquid crystal display (IPS-LCD) is also disclosed. The IPS-LCD includes a storage capacitor consisting of storage-capacitor portions of the common and data electrode structures, which is disposed outside the pixel region so as to enhance the aperture ratio of the pixel region.

Abstract translation: 公开了通过相同的光掩模和光刻工艺来形成公共和数据电极的像素部分来形成平面内切换模式液晶显示器（IPS-LCD）的工艺。 因此，可以避免不对准。 还公开了一种面内切换模式液晶显示器（IPS-LCD）。 IPS-LCD包括由公共数据电极结构的存储电容器部分组成的存储电容器，其设置在像素区域的外部，以增强像素区域的开口率。

公开(公告)号：US06403418B2

公开(公告)日：2002-06-11

申请号：US09551535

申请日：2000-04-18

Applicant: Shiou-Yu Wang ,  Jia-Shyong Cheng ,  Tean-Sen Jen ,  Ming-Teng Hsieh

Inventor： Shiou-Yu Wang ,  Jia-Shyong Cheng ,  Tean-Sen Jen ,  Ming-Teng Hsieh

IPC: H01L218242

CPC classification number: H01L28/91 ,  H01L21/3143 ,  H01L21/31604 ,  H01L27/10855

Abstract: A method of fabricating cup shape cylindrical capacitor of high density Dynamic Random Access Memory (DRAM) cells is disclosed. The cup shape capacitor shape is achieved by first depositing a first polysilicon layer on a silicon substrate; a third dielectric layer is then formed overlaying the first polysilicon layer, and defined third dielectric crowns by the conventional lithography and etching techniques; a second polysilicon layer is deposited overlaying the third dielectric crowns and first polysilicon layer; the first polysilicon and second polysilicon layers are then vertically anisotropically etchback to define storage nodes of the cylindrical capacitors; the third dielectric crowns are removed; finally, the capacitor dielectric layer and the polysilicon top plate of the capacitor are formed to complete the cup shape cylindrical capacitor formation for high density DRAM applications.

Abstract translation: 公开了一种制造高密度动态随机存取存储器（DRAM）单元的杯形圆柱形电容器的方法。 杯状电容器形状通过首先在硅衬底上沉积第一多晶硅层来实现; 然后通过常规的光刻和蚀刻技术形成覆盖第一多晶硅层和限定的第三介电冠的第三介电层; 沉积覆盖第三介电冠和第一多晶硅层的第二多晶硅层; 然后第一多晶硅和第二多晶硅层垂直各向异性回蚀以限定圆柱形电容器的存储节点; 去除第三介质冠; 最后，电容器的电容器电介质层和多晶硅顶板形成为完成用于高密度DRAM应用的杯形圆柱形电容器形成。